IB/mlx5: Support 4k UAR for libmlx5

[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en.h

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h
index 951dbd58594dcd3b32b680f752c1105132d85ba8..a473cea10c16eca565101dd550762f853ce2238b 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h
@@ -465,7 +465,6 @@ struct mlx5e_sq {
        /* read only */
        struct mlx5_wq_cyc         wq;
        u32                        dma_fifo_mask;
-       void __iomem              *uar_map;
        struct netdev_queue       *txq;
        u32                        sqn;
        u16                        bf_buf_size;
@@ -479,7 +478,7 @@ struct mlx5e_sq {
 
        /* control path */
        struct mlx5_wq_ctrl        wq_ctrl;
-       struct mlx5_uar            uar;
+       struct mlx5_sq_bfreg       bfreg;
        struct mlx5e_channel      *channel;
        int                        tc;
        u32                        rate_limit;
@@ -806,7 +805,7 @@ void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
                                      struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
 {
-       u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
+       u16 ofst = sq->bf_offset;
 
        /* ensure wqe is visible to device before updating doorbell record */
        dma_wmb();
@@ -818,9 +817,9 @@ static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
         */
        wmb();
        if (bf_sz)
-               __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
+               __iowrite64_copy(sq->bfreg.map + ofst, ctrl, bf_sz);
        else
-               mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
+               mlx5_write64((__be32 *)ctrl, sq->bfreg.map + ofst, NULL);
        /* flush the write-combining mapped buffer */
        wmb();
 
@@ -832,7 +831,7 @@ static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
        struct mlx5_core_cq *mcq;
 
        mcq = &cq->mcq;
-       mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
+       mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
 }
 
 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)