i40e/i40evf: Don't bother setting the CLEARPBA bit

[sfrench/cifs-2.6.git] / drivers / net / ethernet / intel / i40evf / i40e_txrx.c

diff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c
index 3fd7e9731f49913d05dae486754fe5683a3f738f..34d898f0adaae3d4f7d9f18a4d5641fb3108baba 100644 (file)
--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c
+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c
@@ -1464,8 +1464,17 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr)
 {
        u32 val;
 
+       /* We don't bother with setting the CLEARPBA bit as the data sheet
+        * points out doing so is "meaningless since it was already
+        * auto-cleared". The auto-clearing happens when the interrupt is
+        * asserted.
+        *
+        * Hardware errata 28 for also indicates that writing to a
+        * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear
+        * an event in the PBA anyway so we need to rely on the automask
+        * to hold pending events for us until the interrupt is re-enabled
+        */
        val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
-             I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
              (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
              (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);