Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6

[sfrench/cifs-2.6.git] / drivers / net / e1000e / hw.h

diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h
index 8bdcd5f24eff1b4c3d99e3ca7cb99b7ef2c9ecbd..a419b0715985d32c9b937dde9c86397756441beb 100644 (file)
--- a/drivers/net/e1000e/hw.h
+++ b/drivers/net/e1000e/hw.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel PRO/1000 Linux driver
-  Copyright(c) 1999 - 2009 Intel Corporation.
+  Copyright(c) 1999 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -208,6 +208,8 @@ enum e1e_registers {
 
        E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
        E1000_MANC2H    = 0x05860, /* Management Control To Host - RW */
+       E1000_MDEF_BASE = 0x05890, /* Management Decision Filters */
+#define E1000_MDEF(_n)   (E1000_MDEF_BASE + ((_n) * 4))
        E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
        E1000_GCR       = 0x05B00, /* PCI-Ex Control */
        E1000_GCR2      = 0x05B64, /* PCI-Ex Control #2 */
@@ -215,7 +217,10 @@ enum e1e_registers {
        E1000_SWSM      = 0x05B50, /* SW Semaphore */
        E1000_FWSM      = 0x05B54, /* FW Semaphore */
        E1000_SWSM2     = 0x05B58, /* Driver-only SW semaphore */
-       E1000_CRC_OFFSET = 0x05F50, /* CRC Offset register */
+       E1000_FFLT_DBG  = 0x05F04, /* Debug Register */
+       E1000_PCH_RAICC_BASE = 0x05F50, /* Receive Address Initial CRC */
+#define E1000_PCH_RAICC(_n)    (E1000_PCH_RAICC_BASE + ((_n) * 4))
+#define E1000_CRC_OFFSET       E1000_PCH_RAICC_BASE
        E1000_HICR      = 0x08F00, /* Host Interface Control */
 };
 
@@ -301,13 +306,14 @@ enum e1e_registers {
 #define E1000_KMRNCTRLSTA_OFFSET       0x001F0000
 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
 #define E1000_KMRNCTRLSTA_REN          0x00200000
+#define E1000_KMRNCTRLSTA_CTRL_OFFSET  0x1    /* Kumeran Control */
 #define E1000_KMRNCTRLSTA_DIAG_OFFSET  0x3    /* Kumeran Diagnostic */
 #define E1000_KMRNCTRLSTA_TIMEOUTS     0x4    /* Kumeran Timeouts */
 #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9    /* Kumeran InBand Parameters */
 #define E1000_KMRNCTRLSTA_DIAG_NELPBK  0x1000 /* Nearend Loopback mode */
 #define E1000_KMRNCTRLSTA_K1_CONFIG    0x7
-#define E1000_KMRNCTRLSTA_K1_ENABLE    0x140E
-#define E1000_KMRNCTRLSTA_K1_DISABLE   0x1400
+#define E1000_KMRNCTRLSTA_K1_ENABLE    0x0002
+#define E1000_KMRNCTRLSTA_HD_CTRL      0x0002
 
 #define IFE_PHY_EXTENDED_STATUS_CONTROL        0x10
 #define IFE_PHY_SPECIAL_CONTROL                0x11 /* 100BaseTx PHY Special Control */
@@ -380,10 +386,13 @@ enum e1e_registers {
 #define E1000_DEV_ID_ICH10_R_BM_V              0x10CE
 #define E1000_DEV_ID_ICH10_D_BM_LM             0x10DE
 #define E1000_DEV_ID_ICH10_D_BM_LF             0x10DF
+#define E1000_DEV_ID_ICH10_D_BM_V              0x1525
 #define E1000_DEV_ID_PCH_M_HV_LM               0x10EA
 #define E1000_DEV_ID_PCH_M_HV_LC               0x10EB
 #define E1000_DEV_ID_PCH_D_HV_DM               0x10EF
 #define E1000_DEV_ID_PCH_D_HV_DC               0x10F0
+#define E1000_DEV_ID_PCH2_LV_LM                        0x1502
+#define E1000_DEV_ID_PCH2_LV_V                 0x1503
 
 #define E1000_REVISION_4 4
 
@@ -403,6 +412,7 @@ enum e1000_mac_type {
        e1000_ich9lan,
        e1000_ich10lan,
        e1000_pchlan,
+       e1000_pch2lan,
 };
 
 enum e1000_media_type {
@@ -439,6 +449,7 @@ enum e1000_phy_type {
        e1000_phy_bm,
        e1000_phy_82578,
        e1000_phy_82577,
+       e1000_phy_82579,
 };
 
 enum e1000_bus_width {
@@ -828,6 +839,7 @@ struct e1000_mac_info {
        u8  forced_speed_duplex;
 
        bool adaptive_ifs;
+       bool has_fwsm;
        bool arc_subsystem_valid;
        bool autoneg;
        bool autoneg_failed;
@@ -898,6 +910,7 @@ struct e1000_fc_info {
        u32 high_water;          /* Flow control high-water mark */
        u32 low_water;           /* Flow control low-water mark */
        u16 pause_time;          /* Flow control pause timer */
+       u16 refresh_time;        /* Flow control refresh timer */
        bool send_xon;           /* Flow control send XON */
        bool strict_ieee;        /* Strict IEEE mode */
        enum e1000_fc_mode current_mode; /* FC mode in effect */
@@ -924,6 +937,7 @@ struct e1000_dev_spec_ich8lan {
        bool kmrn_lock_loss_workaround_enabled;
        struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
        bool nvm_k1_enabled;
+       bool eee_disable;
 };
 
 struct e1000_hw {