Merge tag 'mlx5-updates-2018-05-17' of git://git.kernel.org/pub/scm/linux/kernel...

[sfrench/cifs-2.6.git] / drivers / net / dsa / mv88e6xxx / global1.h

diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h
index 6aee7316fea65cd439facd0e2945daa4d6115a7c..7c791c1da4b98af8cdd2885f91ce18ae119ae1d2 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx/global1.h
+++ b/drivers/net/dsa/mv88e6xxx/global1.h
@@ -201,11 +201,35 @@
 
 /* Offset 0x1C: Global Control 2 */
 #define MV88E6XXX_G1_CTL2                      0x1c
-#define MV88E6XXX_G1_CTL2_NO_CASCADE           0xe000
-#define MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE     0xf000
-#define MV88E6XXX_G1_CTL2_HIST_RX              0x0040
-#define MV88E6XXX_G1_CTL2_HIST_TX              0x0080
-#define MV88E6XXX_G1_CTL2_HIST_RX_TX           0x00c0
+#define MV88E6185_G1_CTL2_CASCADE_PORT_MASK    0xf000
+#define MV88E6185_G1_CTL2_CASCADE_PORT_NONE    0xe000
+#define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI   0xf000
+#define MV88E6352_G1_CTL2_HEADER_TYPE_MASK     0xc000
+#define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG     0x0000
+#define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT     0x4000
+#define MV88E6390_G1_CTL2_HEADER_TYPE_LAG      0x8000
+#define MV88E6352_G1_CTL2_RMU_MODE_MASK                0x3000
+#define MV88E6352_G1_CTL2_RMU_MODE_DISABLED    0x0000
+#define MV88E6352_G1_CTL2_RMU_MODE_PORT_4      0x1000
+#define MV88E6352_G1_CTL2_RMU_MODE_PORT_5      0x2000
+#define MV88E6352_G1_CTL2_RMU_MODE_PORT_6      0x3000
+#define MV88E6085_G1_CTL2_DA_CHECK             0x4000
+#define MV88E6085_G1_CTL2_P10RM                        0x2000
+#define MV88E6085_G1_CTL2_RM_ENABLE            0x1000
+#define MV88E6352_G1_CTL2_DA_CHECK             0x0800
+#define MV88E6390_G1_CTL2_RMU_MODE_MASK                0x0700
+#define MV88E6390_G1_CTL2_RMU_MODE_PORT_0      0x0000
+#define MV88E6390_G1_CTL2_RMU_MODE_PORT_1      0x0100
+#define MV88E6390_G1_CTL2_RMU_MODE_PORT_9      0x0200
+#define MV88E6390_G1_CTL2_RMU_MODE_PORT_10     0x0300
+#define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA     0x0600
+#define MV88E6390_G1_CTL2_RMU_MODE_DISABLED    0x0700
+#define MV88E6390_G1_CTL2_HIST_MODE_MASK       0x00c0
+#define MV88E6390_G1_CTL2_HIST_MODE_RX         0x0040
+#define MV88E6390_G1_CTL2_HIST_MODE_TX         0x0080
+#define MV88E6352_G1_CTL2_CTR_MODE_MASK                0x0060
+#define MV88E6390_G1_CTL2_CTR_MODE             0x0020
+#define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK   0x001f
 
 /* Offset 0x1D: Stats Operation Register */
 #define MV88E6XXX_G1_STATS_OP                  0x1d
@@ -253,6 +277,17 @@ int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
 
+int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip);
+int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
+
+int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
+
+int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip);
+int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip);
+int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip);
+
+int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index);
+
 int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
 int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
                                  unsigned int msecs);