[BNX2]: Enable DMA on 5709.
[sfrench/cifs-2.6.git] / drivers / net / bnx2.c
index 88b33c6ddda8d0aaef1306251b63d7c0211c5e16..3b7ca2a455b4bae1dd7299728bf3c488a70adaf8 100644 (file)
@@ -1778,6 +1778,15 @@ bnx2_init_5709_context(struct bnx2 *bp)
        val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
        val |= (BCM_PAGE_BITS - 8) << 16;
        REG_WR(bp, BNX2_CTX_COMMAND, val);
+       for (i = 0; i < 10; i++) {
+               val = REG_RD(bp, BNX2_CTX_COMMAND);
+               if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
+                       break;
+               udelay(2);
+       }
+       if (val & BNX2_CTX_COMMAND_MEM_INIT)
+               return -EBUSY;
+
        for (i = 0; i < bp->ctx_pages; i++) {
                int j;
 
@@ -1811,6 +1820,7 @@ bnx2_init_context(struct bnx2 *bp)
        vcid = 96;
        while (vcid) {
                u32 vcid_addr, pcid_addr, offset;
+               int i;
 
                vcid--;
 
@@ -1831,16 +1841,20 @@ bnx2_init_context(struct bnx2 *bp)
                        pcid_addr = vcid_addr;
                }
 
-               REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
-               REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
+               for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
+                       vcid_addr += (i << PHY_CTX_SHIFT);
+                       pcid_addr += (i << PHY_CTX_SHIFT);
 
-               /* Zero out the context. */
-               for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
-                       CTX_WR(bp, 0x00, offset, 0);
-               }
+                       REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
+                       REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
 
-               REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
-               REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
+                       /* Zero out the context. */
+                       for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
+                               CTX_WR(bp, 0x00, offset, 0);
+
+                       REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
+                       REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
+               }
        }
 }
 
@@ -3691,9 +3705,11 @@ bnx2_init_chip(struct bnx2 *bp)
 
        /* Initialize context mapping and zero out the quick contexts.  The
         * context block must have already been enabled. */
-       if (CHIP_NUM(bp) == CHIP_NUM_5709)
-               bnx2_init_5709_context(bp);
-       else
+       if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+               rc = bnx2_init_5709_context(bp);
+               if (rc)
+                       return rc;
+       } else
                bnx2_init_context(bp);
 
        if ((rc = bnx2_init_cpus(bp)) != 0)
@@ -3799,6 +3815,11 @@ bnx2_init_chip(struct bnx2 *bp)
        /* Initialize the receive filter. */
        bnx2_set_rx_mode(bp->dev);
 
+       if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+               val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
+               val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
+               REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
+       }
        rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
                          0);
 
@@ -4786,19 +4807,6 @@ bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
 
        bnx2_netif_start(bp);
 }
-
-/* Called with rtnl_lock */
-static void
-bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
-{
-       struct bnx2 *bp = netdev_priv(dev);
-
-       bnx2_netif_stop(bp);
-       vlan_group_set_device(bp->vlgrp, vid, NULL);
-       bnx2_set_rx_mode(dev);
-
-       bnx2_netif_start(bp);
-}
 #endif
 
 /* Called with netif_tx_lock.
@@ -6453,7 +6461,6 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
        dev->watchdog_timeo = TX_TIMEOUT;
 #ifdef BCM_VLAN
        dev->vlan_rx_register = bnx2_vlan_rx_register;
-       dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
 #endif
        dev->poll = bnx2_poll;
        dev->ethtool_ops = &bnx2_ethtool_ops;