Merge branches 'arm/omap', 'arm/exynos', 'arm/smmu', 'arm/mediatek', 'arm/qcom',...

[sfrench/cifs-2.6.git] / drivers / iommu / ipmmu-vmsa.c

diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
index ad0098c0c87c7544f18b70c0bd9dc43913ca0478..9da8309f71708f213f91dbe99374681e0da3f652 100644 (file)
--- a/drivers/iommu/ipmmu-vmsa.c
+++ b/drivers/iommu/ipmmu-vmsa.c
@@ -49,6 +49,7 @@ struct ipmmu_features {
        bool setup_imbuscr;
        bool twobit_imttbcr_sl0;
        bool reserved_context;
+       bool cache_snoop;
 };
 
 struct ipmmu_vmsa_device {
@@ -115,45 +116,44 @@ static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev)
 #define IMTTBCR                                0x0008
 #define IMTTBCR_EAE                    (1 << 31)
 #define IMTTBCR_PMB                    (1 << 30)
-#define IMTTBCR_SH1_NON_SHAREABLE      (0 << 28)
-#define IMTTBCR_SH1_OUTER_SHAREABLE    (2 << 28)
-#define IMTTBCR_SH1_INNER_SHAREABLE    (3 << 28)
-#define IMTTBCR_SH1_MASK               (3 << 28)
-#define IMTTBCR_ORGN1_NC               (0 << 26)
-#define IMTTBCR_ORGN1_WB_WA            (1 << 26)
-#define IMTTBCR_ORGN1_WT               (2 << 26)
-#define IMTTBCR_ORGN1_WB               (3 << 26)
-#define IMTTBCR_ORGN1_MASK             (3 << 26)
-#define IMTTBCR_IRGN1_NC               (0 << 24)
-#define IMTTBCR_IRGN1_WB_WA            (1 << 24)
-#define IMTTBCR_IRGN1_WT               (2 << 24)
-#define IMTTBCR_IRGN1_WB               (3 << 24)
-#define IMTTBCR_IRGN1_MASK             (3 << 24)
+#define IMTTBCR_SH1_NON_SHAREABLE      (0 << 28)       /* R-Car Gen2 only */
+#define IMTTBCR_SH1_OUTER_SHAREABLE    (2 << 28)       /* R-Car Gen2 only */
+#define IMTTBCR_SH1_INNER_SHAREABLE    (3 << 28)       /* R-Car Gen2 only */
+#define IMTTBCR_SH1_MASK               (3 << 28)       /* R-Car Gen2 only */
+#define IMTTBCR_ORGN1_NC               (0 << 26)       /* R-Car Gen2 only */
+#define IMTTBCR_ORGN1_WB_WA            (1 << 26)       /* R-Car Gen2 only */
+#define IMTTBCR_ORGN1_WT               (2 << 26)       /* R-Car Gen2 only */
+#define IMTTBCR_ORGN1_WB               (3 << 26)       /* R-Car Gen2 only */
+#define IMTTBCR_ORGN1_MASK             (3 << 26)       /* R-Car Gen2 only */
+#define IMTTBCR_IRGN1_NC               (0 << 24)       /* R-Car Gen2 only */
+#define IMTTBCR_IRGN1_WB_WA            (1 << 24)       /* R-Car Gen2 only */
+#define IMTTBCR_IRGN1_WT               (2 << 24)       /* R-Car Gen2 only */
+#define IMTTBCR_IRGN1_WB               (3 << 24)       /* R-Car Gen2 only */
+#define IMTTBCR_IRGN1_MASK             (3 << 24)       /* R-Car Gen2 only */
 #define IMTTBCR_TSZ1_MASK              (7 << 16)
 #define IMTTBCR_TSZ1_SHIFT             16
-#define IMTTBCR_SH0_NON_SHAREABLE      (0 << 12)
-#define IMTTBCR_SH0_OUTER_SHAREABLE    (2 << 12)
-#define IMTTBCR_SH0_INNER_SHAREABLE    (3 << 12)
-#define IMTTBCR_SH0_MASK               (3 << 12)
-#define IMTTBCR_ORGN0_NC               (0 << 10)
-#define IMTTBCR_ORGN0_WB_WA            (1 << 10)
-#define IMTTBCR_ORGN0_WT               (2 << 10)
-#define IMTTBCR_ORGN0_WB               (3 << 10)
-#define IMTTBCR_ORGN0_MASK             (3 << 10)
-#define IMTTBCR_IRGN0_NC               (0 << 8)
-#define IMTTBCR_IRGN0_WB_WA            (1 << 8)
-#define IMTTBCR_IRGN0_WT               (2 << 8)
-#define IMTTBCR_IRGN0_WB               (3 << 8)
-#define IMTTBCR_IRGN0_MASK             (3 << 8)
+#define IMTTBCR_SH0_NON_SHAREABLE      (0 << 12)       /* R-Car Gen2 only */
+#define IMTTBCR_SH0_OUTER_SHAREABLE    (2 << 12)       /* R-Car Gen2 only */
+#define IMTTBCR_SH0_INNER_SHAREABLE    (3 << 12)       /* R-Car Gen2 only */
+#define IMTTBCR_SH0_MASK               (3 << 12)       /* R-Car Gen2 only */
+#define IMTTBCR_ORGN0_NC               (0 << 10)       /* R-Car Gen2 only */
+#define IMTTBCR_ORGN0_WB_WA            (1 << 10)       /* R-Car Gen2 only */
+#define IMTTBCR_ORGN0_WT               (2 << 10)       /* R-Car Gen2 only */
+#define IMTTBCR_ORGN0_WB               (3 << 10)       /* R-Car Gen2 only */
+#define IMTTBCR_ORGN0_MASK             (3 << 10)       /* R-Car Gen2 only */
+#define IMTTBCR_IRGN0_NC               (0 << 8)        /* R-Car Gen2 only */
+#define IMTTBCR_IRGN0_WB_WA            (1 << 8)        /* R-Car Gen2 only */
+#define IMTTBCR_IRGN0_WT               (2 << 8)        /* R-Car Gen2 only */
+#define IMTTBCR_IRGN0_WB               (3 << 8)        /* R-Car Gen2 only */
+#define IMTTBCR_IRGN0_MASK             (3 << 8)        /* R-Car Gen2 only */
+#define IMTTBCR_SL0_TWOBIT_LVL_3       (0 << 6)        /* R-Car Gen3 only */
+#define IMTTBCR_SL0_TWOBIT_LVL_2       (1 << 6)        /* R-Car Gen3 only */
+#define IMTTBCR_SL0_TWOBIT_LVL_1       (2 << 6)        /* R-Car Gen3 only */
 #define IMTTBCR_SL0_LVL_2              (0 << 4)
 #define IMTTBCR_SL0_LVL_1              (1 << 4)
 #define IMTTBCR_TSZ0_MASK              (7 << 0)
 #define IMTTBCR_TSZ0_SHIFT             O
 
-#define IMTTBCR_SL0_TWOBIT_LVL_3       (0 << 6)
-#define IMTTBCR_SL0_TWOBIT_LVL_2       (1 << 6)
-#define IMTTBCR_SL0_TWOBIT_LVL_1       (2 << 6)
-
 #define IMBUSCR                                0x000c
 #define IMBUSCR_DVM                    (1 << 2)
 #define IMBUSCR_BUSSEL_SYS             (0 << 0)
@@ -361,16 +361,16 @@ static void ipmmu_tlb_flush_all(void *cookie)
        ipmmu_tlb_invalidate(domain);
 }
 
-static void ipmmu_tlb_add_flush(unsigned long iova, size_t size,
-                               size_t granule, bool leaf, void *cookie)
+static void ipmmu_tlb_flush(unsigned long iova, size_t size,
+                               size_t granule, void *cookie)
 {
-       /* The hardware doesn't support selective TLB flush. */
+       ipmmu_tlb_flush_all(cookie);
 }
 
-static const struct iommu_gather_ops ipmmu_gather_ops = {
+static const struct iommu_flush_ops ipmmu_flush_ops = {
        .tlb_flush_all = ipmmu_tlb_flush_all,
-       .tlb_add_flush = ipmmu_tlb_add_flush,
-       .tlb_sync = ipmmu_tlb_flush_all,
+       .tlb_flush_walk = ipmmu_tlb_flush,
+       .tlb_flush_leaf = ipmmu_tlb_flush,
 };
 
 /* -----------------------------------------------------------------------------
@@ -422,17 +422,19 @@ static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain)
 
        /*
         * TTBCR
-        * We use long descriptors with inner-shareable WBWA tables and allocate
-        * the whole 32-bit VA space to TTBR0.
+        * We use long descriptors and allocate the whole 32-bit VA space to
+        * TTBR0.
         */
        if (domain->mmu->features->twobit_imttbcr_sl0)
                tmp = IMTTBCR_SL0_TWOBIT_LVL_1;
        else
                tmp = IMTTBCR_SL0_LVL_1;
 
-       ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE |
-                            IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
-                            IMTTBCR_IRGN0_WB_WA | tmp);
+       if (domain->mmu->features->cache_snoop)
+               tmp |= IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
+                      IMTTBCR_IRGN0_WB_WA;
+
+       ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE | tmp);
 
        /* MAIR0 */
        ipmmu_ctx_write_root(domain, IMMAIR0,
@@ -480,7 +482,7 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
        domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K;
        domain->cfg.ias = 32;
        domain->cfg.oas = 40;
-       domain->cfg.tlb = &ipmmu_gather_ops;
+       domain->cfg.tlb = &ipmmu_flush_ops;
        domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32);
        domain->io_domain.geometry.force_aperture = true;
        /*
@@ -733,14 +735,14 @@ static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova,
 }
 
 static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova,
-                         size_t size)
+                         size_t size, struct iommu_iotlb_gather *gather)
 {
        struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 
-       return domain->iop->unmap(domain->iop, iova, size);
+       return domain->iop->unmap(domain->iop, iova, size, gather);
 }
 
-static void ipmmu_iotlb_sync(struct iommu_domain *io_domain)
+static void ipmmu_flush_iotlb_all(struct iommu_domain *io_domain)
 {
        struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 
@@ -748,6 +750,12 @@ static void ipmmu_iotlb_sync(struct iommu_domain *io_domain)
                ipmmu_tlb_flush_all(domain);
 }
 
+static void ipmmu_iotlb_sync(struct iommu_domain *io_domain,
+                            struct iommu_iotlb_gather *gather)
+{
+       ipmmu_flush_iotlb_all(io_domain);
+}
+
 static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain,
                                      dma_addr_t iova)
 {
@@ -957,7 +965,7 @@ static const struct iommu_ops ipmmu_ops = {
        .detach_dev = ipmmu_detach_device,
        .map = ipmmu_map,
        .unmap = ipmmu_unmap,
-       .flush_iotlb_all = ipmmu_iotlb_sync,
+       .flush_iotlb_all = ipmmu_flush_iotlb_all,
        .iotlb_sync = ipmmu_iotlb_sync,
        .iova_to_phys = ipmmu_iova_to_phys,
        .add_device = ipmmu_add_device,
@@ -988,6 +996,7 @@ static const struct ipmmu_features ipmmu_features_default = {
        .setup_imbuscr = true,
        .twobit_imttbcr_sl0 = false,
        .reserved_context = false,
+       .cache_snoop = true,
 };
 
 static const struct ipmmu_features ipmmu_features_rcar_gen3 = {
@@ -998,6 +1007,7 @@ static const struct ipmmu_features ipmmu_features_rcar_gen3 = {
        .setup_imbuscr = false,
        .twobit_imttbcr_sl0 = true,
        .reserved_context = true,
+       .cache_snoop = false,
 };
 
 static const struct of_device_id ipmmu_of_ids[] = {