Merge tag 'nios2-v4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/lftan...

[sfrench/cifs-2.6.git] / drivers / infiniband / hw / hfi1 / pcie.c

diff --git a/drivers/infiniband/hw/hfi1/pcie.c b/drivers/infiniband/hw/hfi1/pcie.c
index e39e01b793823cad3274429cfe1115337c6bdf0a..93faf86d54b620fb2cc621844932d811c17868dd 100644 (file)
--- a/drivers/infiniband/hw/hfi1/pcie.c
+++ b/drivers/infiniband/hw/hfi1/pcie.c
@@ -240,36 +240,6 @@ void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd)
                iounmap(dd->piobase);
 }
 
-/*
- * Do a Function Level Reset (FLR) on the device.
- * Based on static function drivers/pci/pci.c:pcie_flr().
- */
-void hfi1_pcie_flr(struct hfi1_devdata *dd)
-{
-       int i;
-       u16 status;
-
-       /* no need to check for the capability - we know the device has it */
-
-       /* wait for Transaction Pending bit to clear, at most a few ms */
-       for (i = 0; i < 4; i++) {
-               if (i)
-                       msleep((1 << (i - 1)) * 100);
-
-               pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVSTA, &status);
-               if (!(status & PCI_EXP_DEVSTA_TRPND))
-                       goto clear;
-       }
-
-       dd_dev_err(dd, "Transaction Pending bit is not clearing, proceeding with reset anyway\n");
-
-clear:
-       pcie_capability_set_word(dd->pcidev, PCI_EXP_DEVCTL,
-                                PCI_EXP_DEVCTL_BCR_FLR);
-       /* PCIe spec requires the function to be back within 100ms */
-       msleep(100);
-}
-
 static void msix_setup(struct hfi1_devdata *dd, int pos, u32 *msixcnt,
                       struct hfi1_msix_entry *hfi1_msix_entry)
 {