Merge commit 'v2.6.28-rc9' into x86/apic

[sfrench/cifs-2.6.git] / drivers / gpu / drm / radeon / radeon_drv.h

diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 4dbb813910c3f85060bd956998d7a3a85a63a0b6..3bbb871b25d5102a2b6d832702cc55bc338a70ea 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -287,7 +287,6 @@ typedef struct drm_radeon_private {
        unsigned long gart_textures_offset;
 
        drm_local_map_t *sarea;
-       drm_local_map_t *mmio;
        drm_local_map_t *cp_ring;
        drm_local_map_t *ring_rptr;
        drm_local_map_t *gart_textures;
@@ -300,7 +299,6 @@ typedef struct drm_radeon_private {
        atomic_t swi_emitted;
        int vblank_crtc;
        uint32_t irq_enable_reg;
-       int irq_enabled;
        uint32_t r500_disp_irq_reg;
 
        struct radeon_surface surfaces[RADEON_MAX_SURFACES];
@@ -318,6 +316,7 @@ typedef struct drm_radeon_private {
 
        int num_gb_pipes;
        int track_flush;
+       drm_local_map_t *mmio;
 } drm_radeon_private_t;
 
 typedef struct drm_radeon_buf_priv {
@@ -447,12 +446,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
  * handling, not bus mastering itself.
  */
 #define RADEON_BUS_CNTL                        0x0030
-/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */
+/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 #      define RADEON_BUS_MASTER_DIS            (1 << 6)
-/* rs400, rs690/rs740 */
-#      define RS400_BUS_MASTER_DIS             (1 << 14)
-#      define RS400_MSI_REARM                  (1 << 20)
-/* see RS480_MSI_REARM in AIC_CNTL for rs480 */
+/* rs600/rs690/rs740 */
+#      define RS600_BUS_MASTER_DIS             (1 << 14)
+#      define RS600_MSI_REARM                  (1 << 20)
+/* see RS400_MSI_REARM in AIC_CNTL for rs480 */
 
 #define RADEON_BUS_CNTL1               0x0034
 #      define RADEON_PMI_BM_DIS                (1 << 2)
@@ -937,7 +936,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 
 #define RADEON_AIC_CNTL                        0x01d0
 #      define RADEON_PCIGART_TRANSLATE_EN      (1 << 0)
-#      define RS480_MSI_REARM                  (1 << 3)
+#      define RS400_MSI_REARM                  (1 << 3)
 #define RADEON_AIC_STAT                        0x01d4
 #define RADEON_AIC_PT_BASE             0x01d8
 #define RADEON_AIC_LO_ADDR             0x01dc