Merge tag 'v2.6.35-rc6' into drm-radeon-next
[sfrench/cifs-2.6.git] / drivers / gpu / drm / radeon / radeon_device.c
index dd279da90546ee03929b02b8bd7095683ef31caf..0fea894fc1271d428759b26fb8642a22b8394a71 100644 (file)
@@ -415,6 +415,22 @@ static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
        return r;
 }
 
+static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
+{
+       struct radeon_device *rdev = info->dev->dev_private;
+
+       WREG32_IO(reg*4, val);
+}
+
+static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
+{
+       struct radeon_device *rdev = info->dev->dev_private;
+       uint32_t r;
+
+       r = RREG32_IO(reg*4);
+       return r;
+}
+
 int radeon_atombios_init(struct radeon_device *rdev)
 {
        struct card_info *atom_card_info =
@@ -427,6 +443,15 @@ int radeon_atombios_init(struct radeon_device *rdev)
        atom_card_info->dev = rdev->ddev;
        atom_card_info->reg_read = cail_reg_read;
        atom_card_info->reg_write = cail_reg_write;
+       /* needed for iio ops */
+       if (rdev->rio_mem) {
+               atom_card_info->ioreg_read = cail_ioreg_read;
+               atom_card_info->ioreg_write = cail_ioreg_write;
+       } else {
+               DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
+               atom_card_info->ioreg_read = cail_reg_read;
+               atom_card_info->ioreg_write = cail_reg_write;
+       }
        atom_card_info->mc_read = cail_mc_read;
        atom_card_info->mc_write = cail_mc_write;
        atom_card_info->pll_read = cail_pll_read;
@@ -573,7 +598,7 @@ int radeon_device_init(struct radeon_device *rdev,
                       struct pci_dev *pdev,
                       uint32_t flags)
 {
-       int r;
+       int r, i;
        int dma_bits;
 
        rdev->shutdown = false;
@@ -650,8 +675,8 @@ int radeon_device_init(struct radeon_device *rdev,
 
        /* Registers mapping */
        /* TODO: block userspace mapping of io register */
-       rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
-       rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
+       rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
+       rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
        rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
        if (rdev->rmmio == NULL) {
                return -ENOMEM;
@@ -659,6 +684,17 @@ int radeon_device_init(struct radeon_device *rdev,
        DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
        DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 
+       /* io port mapping */
+       for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+               if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
+                       rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
+                       rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
+                       break;
+               }
+       }
+       if (rdev->rio_mem == NULL)
+               DRM_ERROR("Unable to find PCI I/O BAR\n");
+
        /* if we have > 1 VGA cards, then disable the radeon VGA resources */
        /* this will fail for cards that aren't VGA class devices, just
         * ignore it */
@@ -701,6 +737,8 @@ void radeon_device_fini(struct radeon_device *rdev)
        destroy_workqueue(rdev->wq);
        vga_switcheroo_unregister_client(rdev->pdev);
        vga_client_register(rdev->pdev, NULL, NULL, NULL);
+       pci_iounmap(rdev->pdev, rdev->rio_mem);
+       rdev->rio_mem = NULL;
        iounmap(rdev->rmmio);
        rdev->rmmio = NULL;
 }