drm/radeon/kms: fix regression rendering issue on R6XX/R7XX

[sfrench/cifs-2.6.git] / drivers / gpu / drm / radeon / radeon_asic.h

diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index c3532c7a6f3f04f74d26d6ef97ece8fea7da053e..05ee1aeac3fdce21cd72f3735c156be2c0ab2198 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -31,10 +31,14 @@
 /*
  * common functions
  */
+uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
+uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
 
+uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
+uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
 
@@ -73,6 +77,11 @@ int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
 void r100_bandwidth_update(struct radeon_device *rdev);
 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 int r100_ring_test(struct radeon_device *rdev);
+void r100_hpd_init(struct radeon_device *rdev);
+void r100_hpd_fini(struct radeon_device *rdev);
+bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
+void r100_hpd_set_polarity(struct radeon_device *rdev,
+                          enum radeon_hpd_id hpd);
 
 static struct radeon_asic r100_asic = {
        .init = &r100_init,
@@ -95,13 +104,20 @@ static struct radeon_asic r100_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = NULL,
        .copy = &r100_copy_blit,
+       .get_engine_clock = &radeon_legacy_get_engine_clock,
        .set_engine_clock = &radeon_legacy_set_engine_clock,
+       .get_memory_clock = &radeon_legacy_get_memory_clock,
        .set_memory_clock = NULL,
        .set_pcie_lanes = NULL,
        .set_clock_gating = &radeon_legacy_set_clock_gating,
        .set_surface_reg = r100_set_surface_reg,
        .clear_surface_reg = r100_clear_surface_reg,
        .bandwidth_update = &r100_bandwidth_update,
+       .hpd_init = &r100_hpd_init,
+       .hpd_fini = &r100_hpd_fini,
+       .hpd_sense = &r100_hpd_sense,
+       .hpd_set_polarity = &r100_hpd_set_polarity,
+       .ioctl_wait_idle = NULL,
 };
 
 
@@ -148,13 +164,20 @@ static struct radeon_asic r300_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = &r300_copy_dma,
        .copy = &r100_copy_blit,
+       .get_engine_clock = &radeon_legacy_get_engine_clock,
        .set_engine_clock = &radeon_legacy_set_engine_clock,
+       .get_memory_clock = &radeon_legacy_get_memory_clock,
        .set_memory_clock = NULL,
        .set_pcie_lanes = &rv370_set_pcie_lanes,
        .set_clock_gating = &radeon_legacy_set_clock_gating,
        .set_surface_reg = r100_set_surface_reg,
        .clear_surface_reg = r100_clear_surface_reg,
        .bandwidth_update = &r100_bandwidth_update,
+       .hpd_init = &r100_hpd_init,
+       .hpd_fini = &r100_hpd_fini,
+       .hpd_sense = &r100_hpd_sense,
+       .hpd_set_polarity = &r100_hpd_set_polarity,
+       .ioctl_wait_idle = NULL,
 };
 
 /*
@@ -185,13 +208,20 @@ static struct radeon_asic r420_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = &r300_copy_dma,
        .copy = &r100_copy_blit,
+       .get_engine_clock = &radeon_atom_get_engine_clock,
        .set_engine_clock = &radeon_atom_set_engine_clock,
+       .get_memory_clock = &radeon_atom_get_memory_clock,
        .set_memory_clock = &radeon_atom_set_memory_clock,
        .set_pcie_lanes = &rv370_set_pcie_lanes,
        .set_clock_gating = &radeon_atom_set_clock_gating,
        .set_surface_reg = r100_set_surface_reg,
        .clear_surface_reg = r100_clear_surface_reg,
        .bandwidth_update = &r100_bandwidth_update,
+       .hpd_init = &r100_hpd_init,
+       .hpd_fini = &r100_hpd_fini,
+       .hpd_sense = &r100_hpd_sense,
+       .hpd_set_polarity = &r100_hpd_set_polarity,
+       .ioctl_wait_idle = NULL,
 };
 
 
@@ -227,13 +257,20 @@ static struct radeon_asic rs400_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = &r300_copy_dma,
        .copy = &r100_copy_blit,
+       .get_engine_clock = &radeon_legacy_get_engine_clock,
        .set_engine_clock = &radeon_legacy_set_engine_clock,
+       .get_memory_clock = &radeon_legacy_get_memory_clock,
        .set_memory_clock = NULL,
        .set_pcie_lanes = NULL,
        .set_clock_gating = &radeon_legacy_set_clock_gating,
        .set_surface_reg = r100_set_surface_reg,
        .clear_surface_reg = r100_clear_surface_reg,
        .bandwidth_update = &r100_bandwidth_update,
+       .hpd_init = &r100_hpd_init,
+       .hpd_fini = &r100_hpd_fini,
+       .hpd_sense = &r100_hpd_sense,
+       .hpd_set_polarity = &r100_hpd_set_polarity,
+       .ioctl_wait_idle = NULL,
 };
 
 
@@ -252,6 +289,12 @@ int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 void rs600_bandwidth_update(struct radeon_device *rdev);
+void rs600_hpd_init(struct radeon_device *rdev);
+void rs600_hpd_fini(struct radeon_device *rdev);
+bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
+void rs600_hpd_set_polarity(struct radeon_device *rdev,
+                           enum radeon_hpd_id hpd);
+
 static struct radeon_asic rs600_asic = {
        .init = &rs600_init,
        .fini = &rs600_fini,
@@ -273,11 +316,18 @@ static struct radeon_asic rs600_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = &r300_copy_dma,
        .copy = &r100_copy_blit,
+       .get_engine_clock = &radeon_atom_get_engine_clock,
        .set_engine_clock = &radeon_atom_set_engine_clock,
+       .get_memory_clock = &radeon_atom_get_memory_clock,
        .set_memory_clock = &radeon_atom_set_memory_clock,
        .set_pcie_lanes = NULL,
        .set_clock_gating = &radeon_atom_set_clock_gating,
        .bandwidth_update = &rs600_bandwidth_update,
+       .hpd_init = &rs600_hpd_init,
+       .hpd_fini = &rs600_hpd_fini,
+       .hpd_sense = &rs600_hpd_sense,
+       .hpd_set_polarity = &rs600_hpd_set_polarity,
+       .ioctl_wait_idle = NULL,
 };
 
 
@@ -312,13 +362,20 @@ static struct radeon_asic rs690_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = &r300_copy_dma,
        .copy = &r300_copy_dma,
+       .get_engine_clock = &radeon_atom_get_engine_clock,
        .set_engine_clock = &radeon_atom_set_engine_clock,
+       .get_memory_clock = &radeon_atom_get_memory_clock,
        .set_memory_clock = &radeon_atom_set_memory_clock,
        .set_pcie_lanes = NULL,
        .set_clock_gating = &radeon_atom_set_clock_gating,
        .set_surface_reg = r100_set_surface_reg,
        .clear_surface_reg = r100_clear_surface_reg,
        .bandwidth_update = &rs690_bandwidth_update,
+       .hpd_init = &rs600_hpd_init,
+       .hpd_fini = &rs600_hpd_fini,
+       .hpd_sense = &rs600_hpd_sense,
+       .hpd_set_polarity = &rs600_hpd_set_polarity,
+       .ioctl_wait_idle = NULL,
 };
 
 
@@ -357,13 +414,20 @@ static struct radeon_asic rv515_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = &r300_copy_dma,
        .copy = &r100_copy_blit,
+       .get_engine_clock = &radeon_atom_get_engine_clock,
        .set_engine_clock = &radeon_atom_set_engine_clock,
+       .get_memory_clock = &radeon_atom_get_memory_clock,
        .set_memory_clock = &radeon_atom_set_memory_clock,
        .set_pcie_lanes = &rv370_set_pcie_lanes,
        .set_clock_gating = &radeon_atom_set_clock_gating,
        .set_surface_reg = r100_set_surface_reg,
        .clear_surface_reg = r100_clear_surface_reg,
        .bandwidth_update = &rv515_bandwidth_update,
+       .hpd_init = &rs600_hpd_init,
+       .hpd_fini = &rs600_hpd_fini,
+       .hpd_sense = &rs600_hpd_sense,
+       .hpd_set_polarity = &rs600_hpd_set_polarity,
+       .ioctl_wait_idle = NULL,
 };
 
 
@@ -393,13 +457,20 @@ static struct radeon_asic r520_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = &r300_copy_dma,
        .copy = &r100_copy_blit,
+       .get_engine_clock = &radeon_atom_get_engine_clock,
        .set_engine_clock = &radeon_atom_set_engine_clock,
+       .get_memory_clock = &radeon_atom_get_memory_clock,
        .set_memory_clock = &radeon_atom_set_memory_clock,
        .set_pcie_lanes = &rv370_set_pcie_lanes,
        .set_clock_gating = &radeon_atom_set_clock_gating,
        .set_surface_reg = r100_set_surface_reg,
        .clear_surface_reg = r100_clear_surface_reg,
        .bandwidth_update = &rv515_bandwidth_update,
+       .hpd_init = &rs600_hpd_init,
+       .hpd_fini = &rs600_hpd_fini,
+       .hpd_sense = &rs600_hpd_sense,
+       .hpd_set_polarity = &rs600_hpd_set_polarity,
+       .ioctl_wait_idle = NULL,
 };
 
 /*
@@ -436,6 +507,12 @@ int r600_ring_test(struct radeon_device *rdev);
 int r600_copy_blit(struct radeon_device *rdev,
                   uint64_t src_offset, uint64_t dst_offset,
                   unsigned num_pages, struct radeon_fence *fence);
+void r600_hpd_init(struct radeon_device *rdev);
+void r600_hpd_fini(struct radeon_device *rdev);
+bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
+void r600_hpd_set_polarity(struct radeon_device *rdev,
+                          enum radeon_hpd_id hpd);
+extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
 
 static struct radeon_asic r600_asic = {
        .init = &r600_init,
@@ -451,18 +528,26 @@ static struct radeon_asic r600_asic = {
        .ring_ib_execute = &r600_ring_ib_execute,
        .irq_set = &r600_irq_set,
        .irq_process = &r600_irq_process,
+       .get_vblank_counter = &rs600_get_vblank_counter,
        .fence_ring_emit = &r600_fence_ring_emit,
        .cs_parse = &r600_cs_parse,
        .copy_blit = &r600_copy_blit,
        .copy_dma = &r600_copy_blit,
        .copy = &r600_copy_blit,
+       .get_engine_clock = &radeon_atom_get_engine_clock,
        .set_engine_clock = &radeon_atom_set_engine_clock,
+       .get_memory_clock = &radeon_atom_get_memory_clock,
        .set_memory_clock = &radeon_atom_set_memory_clock,
        .set_pcie_lanes = NULL,
        .set_clock_gating = &radeon_atom_set_clock_gating,
        .set_surface_reg = r600_set_surface_reg,
        .clear_surface_reg = r600_clear_surface_reg,
        .bandwidth_update = &rv515_bandwidth_update,
+       .hpd_init = &r600_hpd_init,
+       .hpd_fini = &r600_hpd_fini,
+       .hpd_sense = &r600_hpd_sense,
+       .hpd_set_polarity = &r600_hpd_set_polarity,
+       .ioctl_wait_idle = r600_ioctl_wait_idle,
 };
 
 /*
@@ -488,18 +573,26 @@ static struct radeon_asic rv770_asic = {
        .ring_ib_execute = &r600_ring_ib_execute,
        .irq_set = &r600_irq_set,
        .irq_process = &r600_irq_process,
+       .get_vblank_counter = &rs600_get_vblank_counter,
        .fence_ring_emit = &r600_fence_ring_emit,
        .cs_parse = &r600_cs_parse,
        .copy_blit = &r600_copy_blit,
        .copy_dma = &r600_copy_blit,
        .copy = &r600_copy_blit,
+       .get_engine_clock = &radeon_atom_get_engine_clock,
        .set_engine_clock = &radeon_atom_set_engine_clock,
+       .get_memory_clock = &radeon_atom_get_memory_clock,
        .set_memory_clock = &radeon_atom_set_memory_clock,
        .set_pcie_lanes = NULL,
        .set_clock_gating = &radeon_atom_set_clock_gating,
        .set_surface_reg = r600_set_surface_reg,
        .clear_surface_reg = r600_clear_surface_reg,
        .bandwidth_update = &rv515_bandwidth_update,
+       .hpd_init = &r600_hpd_init,
+       .hpd_fini = &r600_hpd_fini,
+       .hpd_sense = &r600_hpd_sense,
+       .hpd_set_polarity = &r600_hpd_set_polarity,
+       .ioctl_wait_idle = r600_ioctl_wait_idle,
 };
 
 #endif