Merge tag 'v2.6.35-rc6' into drm-radeon-next

[sfrench/cifs-2.6.git] / drivers / gpu / drm / radeon / radeon.h

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index be8420e65f01b8b15a30249d514ff3b42b31401c..c84f9a311550ae7726709a8bd42258c5207e45cb 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -354,6 +354,7 @@ struct radeon_mc {
        int                     vram_mtrr;
        bool                    vram_is_ddr;
        bool                    igp_sideport_enabled;
+       u64                     gtt_base_align;
 };
 
 bool radeon_combios_sideport_present(struct radeon_device *rdev);
@@ -1048,6 +1049,9 @@ struct radeon_device {
        uint32_t                        pcie_reg_mask;
        radeon_rreg_t                   pciep_rreg;
        radeon_wreg_t                   pciep_wreg;
+       /* io port */
+       void __iomem                    *rio_mem;
+       resource_size_t                 rio_mem_size;
        struct radeon_clock             clock;
        struct radeon_mc                mc;
        struct radeon_gart              gart;
@@ -1084,6 +1088,7 @@ struct radeon_device {
        struct mutex vram_mutex;
 
        /* audio stuff */
+       bool                    audio_enabled;
        struct timer_list       audio_timer;
        int                     audio_channels;
        int                     audio_rate;
@@ -1129,6 +1134,26 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
        }
 }
 
+static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
+{
+       if (reg < rdev->rio_mem_size)
+               return ioread32(rdev->rio_mem + reg);
+       else {
+               iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
+               return ioread32(rdev->rio_mem + RADEON_MM_DATA);
+       }
+}
+
+static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
+{
+       if (reg < rdev->rio_mem_size)
+               iowrite32(v, rdev->rio_mem + reg);
+       else {
+               iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
+               iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
+       }
+}
+
 /*
  * Cast helper
  */
@@ -1167,6 +1192,8 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
                WREG32_PLL(reg, tmp_);                          \
        } while (0)
 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
+#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
+#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
 
 /*
  * Indirect registers accessor