drm/radeon: Unbreak HPD handling for r600+

[sfrench/cifs-2.6.git] / drivers / gpu / drm / radeon / evergreen.c

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index d1b1e0cc3c25b773f32ccc74c9401cf99b363c84..0bf103536404e5dde2d480bf692a496a6865e817 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2188,13 +2188,7 @@ static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
        b.full = dfixed_const(wm->num_heads);
        a.full = dfixed_div(a, b);
 
-       b.full = dfixed_const(1000);
-       c.full = dfixed_const(wm->disp_clk);
-       b.full = dfixed_div(c, b);
-       c.full = dfixed_const(wm->bytes_per_pixel);
-       b.full = dfixed_mul(b, c);
-
-       lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
+       lb_fill_bw = min(dfixed_trunc(a), wm->disp_clk * wm->bytes_per_pixel / 1000);
 
        a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
        b.full = dfixed_const(1000);
@@ -2261,7 +2255,7 @@ static void evergreen_program_watermarks(struct radeon_device *rdev,
        struct drm_display_mode *mode = &radeon_crtc->base.mode;
        struct evergreen_wm_params wm_low, wm_high;
        u32 dram_channels;
-       u32 pixel_period;
+       u32 active_time;
        u32 line_time = 0;
        u32 latency_watermark_a = 0, latency_watermark_b = 0;
        u32 priority_a_mark = 0, priority_b_mark = 0;
@@ -2272,8 +2266,8 @@ static void evergreen_program_watermarks(struct radeon_device *rdev,
        fixed20_12 a, b, c;
 
        if (radeon_crtc->base.enabled && num_heads && mode) {
-               pixel_period = 1000000 / (u32)mode->clock;
-               line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
+               active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+               line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
                priority_a_cnt = 0;
                priority_b_cnt = 0;
                dram_channels = evergreen_get_number_of_dram_channels(rdev);
@@ -2291,7 +2285,7 @@ static void evergreen_program_watermarks(struct radeon_device *rdev,
 
                wm_high.disp_clk = mode->clock;
                wm_high.src_width = mode->crtc_hdisplay;
-               wm_high.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_high.active_time = active_time;
                wm_high.blank_time = line_time - wm_high.active_time;
                wm_high.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -2318,7 +2312,7 @@ static void evergreen_program_watermarks(struct radeon_device *rdev,
 
                wm_low.disp_clk = mode->clock;
                wm_low.src_width = mode->crtc_hdisplay;
-               wm_low.active_time = mode->crtc_hdisplay * pixel_period;
+               wm_low.active_time = active_time;
                wm_low.blank_time = line_time - wm_low.active_time;
                wm_low.interlaced = false;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -4933,7 +4927,7 @@ static void evergreen_irq_ack(struct radeon_device *rdev)
                WREG32(DC_HPD5_INT_CONTROL, tmp);
        }
        if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
-               tmp = RREG32(DC_HPD5_INT_CONTROL);
+               tmp = RREG32(DC_HPD6_INT_CONTROL);
                tmp |= DC_HPDx_INT_ACK;
                WREG32(DC_HPD6_INT_CONTROL, tmp);
        }
@@ -4964,7 +4958,7 @@ static void evergreen_irq_ack(struct radeon_device *rdev)
                WREG32(DC_HPD5_INT_CONTROL, tmp);
        }
        if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
-               tmp = RREG32(DC_HPD5_INT_CONTROL);
+               tmp = RREG32(DC_HPD6_INT_CONTROL);
                tmp |= DC_HPDx_RX_INT_ACK;
                WREG32(DC_HPD6_INT_CONTROL, tmp);
        }