Merge tag 'drm-intel-next-2019-03-20' of git://anongit.freedesktop.org/drm/drm-intel...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_sprite.c
index b56a1a9ad01d2e724715503b545d4396f56f7194..3f2055f70d05123313e769b7e328ed4615973047 100644 (file)
 #include "i915_drv.h"
 #include <drm/drm_color_mgmt.h>
 
+bool is_planar_yuv_format(u32 pixelformat)
+{
+       switch (pixelformat) {
+       case DRM_FORMAT_NV12:
+       case DRM_FORMAT_P010:
+       case DRM_FORMAT_P012:
+       case DRM_FORMAT_P016:
+               return true;
+       default:
+               return false;
+       }
+}
+
 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
                             int usecs)
 {
@@ -335,8 +348,8 @@ skl_program_scaler(struct intel_plane *plane,
                                      0, INT_MAX);
 
        /* TODO: handle sub-pixel coordinates */
-       if (plane_state->base.fb->format->format == DRM_FORMAT_NV12 &&
-           !icl_is_hdr_plane(plane)) {
+       if (is_planar_yuv_format(plane_state->base.fb->format->format) &&
+           !icl_is_hdr_plane(dev_priv, plane->id)) {
                y_hphase = skl_scaler_calc_phase(1, hscale, false);
                y_vphase = skl_scaler_calc_phase(1, vscale, false);
 
@@ -518,7 +531,7 @@ skl_program_plane(struct intel_plane *plane,
        I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
                      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
 
-       if (icl_is_hdr_plane(plane)) {
+       if (icl_is_hdr_plane(dev_priv, plane_id)) {
                u32 cus_ctl = 0;
 
                if (linked) {
@@ -542,7 +555,7 @@ skl_program_plane(struct intel_plane *plane,
        if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
                I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
 
-       if (fb->format->is_yuv && icl_is_hdr_plane(plane))
+       if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
                icl_program_input_csc(plane, crtc_state, plane_state);
 
        skl_write_plane_wm(plane, crtc_state);
@@ -609,6 +622,9 @@ skl_disable_plane(struct intel_plane *plane,
 
        spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
+       if (icl_is_hdr_plane(dev_priv, plane_id))
+               I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), 0);
+
        skl_write_plane_wm(plane, crtc_state);
 
        I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
@@ -741,7 +757,12 @@ vlv_update_clrc(const struct intel_plane_state *plane_state)
 
 static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
-       return SP_GAMMA_ENABLE;
+       u32 sprctl = 0;
+
+       if (crtc_state->gamma_enable)
+               sprctl |= SP_GAMMA_ENABLE;
+
+       return sprctl;
 }
 
 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
@@ -916,12 +937,12 @@ vlv_plane_get_hw_state(struct intel_plane *plane,
 
 static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
-       struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
        u32 sprctl = 0;
 
-       sprctl |= SPRITE_GAMMA_ENABLE;
+       if (crtc_state->gamma_enable)
+               sprctl |= SPRITE_GAMMA_ENABLE;
 
-       if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+       if (crtc_state->csc_enable)
                sprctl |= SPRITE_PIPE_CSC_ENABLE;
 
        return sprctl;
@@ -1107,7 +1128,15 @@ g4x_sprite_max_stride(struct intel_plane *plane,
 
 static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
-       return DVS_GAMMA_ENABLE;
+       u32 dvscntr = 0;
+
+       if (crtc_state->gamma_enable)
+               dvscntr |= DVS_GAMMA_ENABLE;
+
+       if (crtc_state->csc_enable)
+               dvscntr |= DVS_PIPE_CSC_ENABLE;
+
+       return dvscntr;
 }
 
 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
@@ -1482,8 +1511,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
                /*
                 * 90/270 is not allowed with RGB64 16:16:16:16 and
                 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
-                * TBD: Add RGB64 case once its added in supported format
-                * list.
                 */
                switch (fb->format->format) {
                case DRM_FORMAT_RGB565:
@@ -1491,6 +1518,10 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
                                break;
                        /* fall through */
                case DRM_FORMAT_C8:
+               case DRM_FORMAT_XRGB16161616F:
+               case DRM_FORMAT_XBGR16161616F:
+               case DRM_FORMAT_ARGB16161616F:
+               case DRM_FORMAT_ABGR16161616F:
                        DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
                                      drm_get_format_name(fb->format->format,
                                                          &format_name));
@@ -1551,10 +1582,10 @@ static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_s
        int src_w = drm_rect_width(&plane_state->base.src) >> 16;
 
        /* Display WA #1106 */
-       if (fb->format->format == DRM_FORMAT_NV12 && src_w & 3 &&
+       if (is_planar_yuv_format(fb->format->format) && src_w & 3 &&
            (rotation == DRM_MODE_ROTATE_270 ||
             rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
-               DRM_DEBUG_KMS("src width must be multiple of 4 for rotated NV12\n");
+               DRM_DEBUG_KMS("src width must be multiple of 4 for rotated planar YUV\n");
                return -EINVAL;
        }
 
@@ -1790,6 +1821,52 @@ static const u32 skl_plane_formats[] = {
        DRM_FORMAT_VYUY,
 };
 
+static const u32 icl_plane_formats[] = {
+       DRM_FORMAT_C8,
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_XBGR8888,
+       DRM_FORMAT_ARGB8888,
+       DRM_FORMAT_ABGR8888,
+       DRM_FORMAT_XRGB2101010,
+       DRM_FORMAT_XBGR2101010,
+       DRM_FORMAT_YUYV,
+       DRM_FORMAT_YVYU,
+       DRM_FORMAT_UYVY,
+       DRM_FORMAT_VYUY,
+       DRM_FORMAT_Y210,
+       DRM_FORMAT_Y212,
+       DRM_FORMAT_Y216,
+       DRM_FORMAT_XVYU2101010,
+       DRM_FORMAT_XVYU12_16161616,
+       DRM_FORMAT_XVYU16161616,
+};
+
+static const u32 icl_hdr_plane_formats[] = {
+       DRM_FORMAT_C8,
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_XBGR8888,
+       DRM_FORMAT_ARGB8888,
+       DRM_FORMAT_ABGR8888,
+       DRM_FORMAT_XRGB2101010,
+       DRM_FORMAT_XBGR2101010,
+       DRM_FORMAT_XRGB16161616F,
+       DRM_FORMAT_XBGR16161616F,
+       DRM_FORMAT_ARGB16161616F,
+       DRM_FORMAT_ABGR16161616F,
+       DRM_FORMAT_YUYV,
+       DRM_FORMAT_YVYU,
+       DRM_FORMAT_UYVY,
+       DRM_FORMAT_VYUY,
+       DRM_FORMAT_Y210,
+       DRM_FORMAT_Y212,
+       DRM_FORMAT_Y216,
+       DRM_FORMAT_XVYU2101010,
+       DRM_FORMAT_XVYU12_16161616,
+       DRM_FORMAT_XVYU16161616,
+};
+
 static const u32 skl_planar_formats[] = {
        DRM_FORMAT_C8,
        DRM_FORMAT_RGB565,
@@ -1806,6 +1883,79 @@ static const u32 skl_planar_formats[] = {
        DRM_FORMAT_NV12,
 };
 
+static const u32 glk_planar_formats[] = {
+       DRM_FORMAT_C8,
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_XBGR8888,
+       DRM_FORMAT_ARGB8888,
+       DRM_FORMAT_ABGR8888,
+       DRM_FORMAT_XRGB2101010,
+       DRM_FORMAT_XBGR2101010,
+       DRM_FORMAT_YUYV,
+       DRM_FORMAT_YVYU,
+       DRM_FORMAT_UYVY,
+       DRM_FORMAT_VYUY,
+       DRM_FORMAT_NV12,
+       DRM_FORMAT_P010,
+       DRM_FORMAT_P012,
+       DRM_FORMAT_P016,
+};
+
+static const u32 icl_planar_formats[] = {
+       DRM_FORMAT_C8,
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_XBGR8888,
+       DRM_FORMAT_ARGB8888,
+       DRM_FORMAT_ABGR8888,
+       DRM_FORMAT_XRGB2101010,
+       DRM_FORMAT_XBGR2101010,
+       DRM_FORMAT_YUYV,
+       DRM_FORMAT_YVYU,
+       DRM_FORMAT_UYVY,
+       DRM_FORMAT_VYUY,
+       DRM_FORMAT_NV12,
+       DRM_FORMAT_P010,
+       DRM_FORMAT_P012,
+       DRM_FORMAT_P016,
+       DRM_FORMAT_Y210,
+       DRM_FORMAT_Y212,
+       DRM_FORMAT_Y216,
+       DRM_FORMAT_XVYU2101010,
+       DRM_FORMAT_XVYU12_16161616,
+       DRM_FORMAT_XVYU16161616,
+};
+
+static const u32 icl_hdr_planar_formats[] = {
+       DRM_FORMAT_C8,
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_XBGR8888,
+       DRM_FORMAT_ARGB8888,
+       DRM_FORMAT_ABGR8888,
+       DRM_FORMAT_XRGB2101010,
+       DRM_FORMAT_XBGR2101010,
+       DRM_FORMAT_XRGB16161616F,
+       DRM_FORMAT_XBGR16161616F,
+       DRM_FORMAT_ARGB16161616F,
+       DRM_FORMAT_ABGR16161616F,
+       DRM_FORMAT_YUYV,
+       DRM_FORMAT_YVYU,
+       DRM_FORMAT_UYVY,
+       DRM_FORMAT_VYUY,
+       DRM_FORMAT_NV12,
+       DRM_FORMAT_P010,
+       DRM_FORMAT_P012,
+       DRM_FORMAT_P016,
+       DRM_FORMAT_Y210,
+       DRM_FORMAT_Y212,
+       DRM_FORMAT_Y216,
+       DRM_FORMAT_XVYU2101010,
+       DRM_FORMAT_XVYU12_16161616,
+       DRM_FORMAT_XVYU16161616,
+};
+
 static const u64 skl_plane_format_modifiers_noccs[] = {
        I915_FORMAT_MOD_Yf_TILED,
        I915_FORMAT_MOD_Y_TILED,
@@ -1945,10 +2095,23 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
        case DRM_FORMAT_UYVY:
        case DRM_FORMAT_VYUY:
        case DRM_FORMAT_NV12:
+       case DRM_FORMAT_P010:
+       case DRM_FORMAT_P012:
+       case DRM_FORMAT_P016:
+       case DRM_FORMAT_Y210:
+       case DRM_FORMAT_Y212:
+       case DRM_FORMAT_Y216:
+       case DRM_FORMAT_XVYU2101010:
+       case DRM_FORMAT_XVYU12_16161616:
+       case DRM_FORMAT_XVYU16161616:
                if (modifier == I915_FORMAT_MOD_Yf_TILED)
                        return true;
                /* fall through */
        case DRM_FORMAT_C8:
+       case DRM_FORMAT_XBGR16161616F:
+       case DRM_FORMAT_ABGR16161616F:
+       case DRM_FORMAT_XRGB16161616F:
+       case DRM_FORMAT_ARGB16161616F:
                if (modifier == DRM_FORMAT_MOD_LINEAR ||
                    modifier == I915_FORMAT_MOD_X_TILED ||
                    modifier == I915_FORMAT_MOD_Y_TILED)
@@ -2085,8 +2248,25 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
                plane->update_slave = icl_update_slave;
 
        if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
-               formats = skl_planar_formats;
-               num_formats = ARRAY_SIZE(skl_planar_formats);
+               if (icl_is_hdr_plane(dev_priv, plane_id)) {
+                       formats = icl_hdr_planar_formats;
+                       num_formats = ARRAY_SIZE(icl_hdr_planar_formats);
+               } else if (INTEL_GEN(dev_priv) >= 11) {
+                       formats = icl_planar_formats;
+                       num_formats = ARRAY_SIZE(icl_planar_formats);
+               } else if (INTEL_GEN(dev_priv) == 10 || IS_GEMINILAKE(dev_priv)) {
+                       formats = glk_planar_formats;
+                       num_formats = ARRAY_SIZE(glk_planar_formats);
+               } else {
+                       formats = skl_planar_formats;
+                       num_formats = ARRAY_SIZE(skl_planar_formats);
+               }
+       } else if (icl_is_hdr_plane(dev_priv, plane_id)) {
+               formats = icl_hdr_plane_formats;
+               num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
+       } else if (INTEL_GEN(dev_priv) >= 11) {
+               formats = icl_plane_formats;
+               num_formats = ARRAY_SIZE(icl_plane_formats);
        } else {
                formats = skl_plane_formats;
                num_formats = ARRAY_SIZE(skl_plane_formats);