Merge tag 'drm-intel-next-2019-03-20' of git://anongit.freedesktop.org/drm/drm-intel...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / intel_display.c

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 41e457d2e8bfea03b3cc0243ed7259f511e08ef5..8574c212b37c4a8b85f537e7511dfdb5af05932e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -595,7 +595,7 @@ i9xx_select_p2_div(const struct intel_limit *limit,
                   const struct intel_crtc_state *crtc_state,
                   int target)
 {
-       struct drm_device *dev = crtc_state->base.crtc->dev;
+       struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 
        if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
                /*
@@ -603,7 +603,7 @@ i9xx_select_p2_div(const struct intel_limit *limit,
                 * We haven't figured out how to reliably set up different
                 * single/dual channel state, if we even can.
                 */
-               if (intel_is_dual_link_lvds(dev))
+               if (intel_is_dual_link_lvds(dev_priv))
                        return limit->p2.p2_fast;
                else
                        return limit->p2.p2_slow;
@@ -951,14 +951,15 @@ chv_find_best_dpll(const struct intel_limit *limit,
        return found;
 }
 
-bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
+bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
                        struct dpll *best_clock)
 {
        int refclk = 100000;
        const struct intel_limit *limit = &intel_limits_bxt;
 
        return chv_find_best_dpll(limit, crtc_state,
-                                 target_clock, refclk, NULL, best_clock);
+                                 crtc_state->port_clock, refclk,
+                                 NULL, best_clock);
 }
 
 bool intel_crtc_active(struct intel_crtc *crtc)
@@ -1621,14 +1622,15 @@ static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s
        }
 
        val &= ~TRANS_INTERLACE_MASK;
-       if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
+       if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
                if (HAS_PCH_IBX(dev_priv) &&
                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
                        val |= TRANS_LEGACY_INTERLACED_ILK;
                else
                        val |= TRANS_INTERLACED;
-       else
+       } else {
                val |= TRANS_PROGRESSIVE;
+       }
 
        I915_WRITE(reg, val | TRANS_ENABLE);
        if (intel_wait_for_register(dev_priv,
@@ -2657,11 +2659,11 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
        case PLANE_CTL_FORMAT_Y216:
                return DRM_FORMAT_Y216;
        case PLANE_CTL_FORMAT_Y410:
-               return DRM_FORMAT_Y410;
+               return DRM_FORMAT_XVYU2101010;
        case PLANE_CTL_FORMAT_Y412:
-               return DRM_FORMAT_Y412;
+               return DRM_FORMAT_XVYU12_16161616;
        case PLANE_CTL_FORMAT_Y416:
-               return DRM_FORMAT_Y416;
+               return DRM_FORMAT_XVYU16161616;
        default:
        case PLANE_CTL_FORMAT_XRGB_8888:
                if (rgb_order) {
@@ -2680,6 +2682,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
                        return DRM_FORMAT_XBGR2101010;
                else
                        return DRM_FORMAT_XRGB2101010;
+       case PLANE_CTL_FORMAT_XRGB_16161616F:
+               if (rgb_order) {
+                       if (alpha)
+                               return DRM_FORMAT_ABGR16161616F;
+                       else
+                               return DRM_FORMAT_XBGR16161616F;
+               } else {
+                       if (alpha)
+                               return DRM_FORMAT_ARGB16161616F;
+                       else
+                               return DRM_FORMAT_XRGB16161616F;
+               }
        }
 }
 
@@ -3575,6 +3589,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
                return PLANE_CTL_FORMAT_XRGB_2101010;
        case DRM_FORMAT_XBGR2101010:
                return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
+       case DRM_FORMAT_XBGR16161616F:
+       case DRM_FORMAT_ABGR16161616F:
+               return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
+       case DRM_FORMAT_XRGB16161616F:
+       case DRM_FORMAT_ARGB16161616F:
+               return PLANE_CTL_FORMAT_XRGB_16161616F;
        case DRM_FORMAT_YUYV:
                return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
        case DRM_FORMAT_YVYU:
@@ -3597,11 +3617,11 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
                return PLANE_CTL_FORMAT_Y212;
        case DRM_FORMAT_Y216:
                return PLANE_CTL_FORMAT_Y216;
-       case DRM_FORMAT_Y410:
+       case DRM_FORMAT_XVYU2101010:
                return PLANE_CTL_FORMAT_Y410;
-       case DRM_FORMAT_Y412:
+       case DRM_FORMAT_XVYU12_16161616:
                return PLANE_CTL_FORMAT_Y412;
-       case DRM_FORMAT_Y416:
+       case DRM_FORMAT_XVYU16161616:
                return PLANE_CTL_FORMAT_Y416;
        default:
                MISSING_CASE(pixel_format);
@@ -3781,6 +3801,8 @@ u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
                        const struct intel_plane_state *plane_state)
 {
+       struct drm_i915_private *dev_priv =
+               to_i915(plane_state->base.plane->dev);
        const struct drm_framebuffer *fb = plane_state->base.fb;
        struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
        u32 plane_color_ctl = 0;
@@ -3788,7 +3810,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
        plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
        plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
 
-       if (fb->format->is_yuv && !icl_is_hdr_plane(plane)) {
+       if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
                if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
                        plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
                else
@@ -5101,13 +5123,14 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 {
        struct intel_plane *intel_plane =
                to_intel_plane(plane_state->base.plane);
+       struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
        struct drm_framebuffer *fb = plane_state->base.fb;
        int ret;
        bool force_detach = !fb || !plane_state->base.visible;
        bool need_scaler = false;
 
        /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
-       if (!icl_is_hdr_plane(intel_plane) &&
+       if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
            fb && is_planar_yuv_format(fb->format->format))
                need_scaler = true;
 
@@ -5140,6 +5163,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
        case DRM_FORMAT_ARGB8888:
        case DRM_FORMAT_XRGB2101010:
        case DRM_FORMAT_XBGR2101010:
+       case DRM_FORMAT_XBGR16161616F:
+       case DRM_FORMAT_ABGR16161616F:
+       case DRM_FORMAT_XRGB16161616F:
+       case DRM_FORMAT_ARGB16161616F:
        case DRM_FORMAT_YUYV:
        case DRM_FORMAT_YVYU:
        case DRM_FORMAT_UYVY:
@@ -5151,9 +5178,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
        case DRM_FORMAT_Y210:
        case DRM_FORMAT_Y212:
        case DRM_FORMAT_Y216:
-       case DRM_FORMAT_Y410:
-       case DRM_FORMAT_Y412:
-       case DRM_FORMAT_Y416:
+       case DRM_FORMAT_XVYU2101010:
+       case DRM_FORMAT_XVYU12_16161616:
+       case DRM_FORMAT_XVYU16161616:
                break;
        default:
                DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -6846,8 +6873,7 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
 static int intel_crtc_compute_config(struct intel_crtc *crtc,
                                     struct intel_crtc_state *pipe_config)
 {
-       struct drm_device *dev = crtc->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
        int clock_limit = dev_priv->max_dotclk_freq;
 
@@ -6897,7 +6923,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
                }
 
                if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
-                   intel_is_dual_link_lvds(dev)) {
+                   intel_is_dual_link_lvds(dev_priv)) {
                        DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
                        return -EINVAL;
                }
@@ -7734,8 +7760,9 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
                        pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
                else
                        pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
-       } else
+       } else {
                pipeconf |= PIPECONF_PROGRESSIVE;
+       }
 
        if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
             crtc_state->limited_color_range)
@@ -7786,8 +7813,7 @@ static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
                                  struct intel_crtc_state *crtc_state)
 {
-       struct drm_device *dev = crtc->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        const struct intel_limit *limit;
        int refclk = 96000;
 
@@ -7800,7 +7826,7 @@ static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
                        DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
                }
 
-               if (intel_is_dual_link_lvds(dev))
+               if (intel_is_dual_link_lvds(dev_priv))
                        limit = &intel_limits_g4x_dual_channel_lvds;
                else
                        limit = &intel_limits_g4x_single_channel_lvds;
@@ -8834,13 +8860,11 @@ static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
        return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
 }
 
-static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
+static void ironlake_compute_dpll(struct intel_crtc *crtc,
                                  struct intel_crtc_state *crtc_state,
                                  struct dpll *reduced_clock)
 {
-       struct drm_crtc *crtc = &intel_crtc->base;
-       struct drm_device *dev = crtc->dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        u32 dpll, fp, fp2;
        int factor;
 
@@ -8849,10 +8873,12 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
        if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
                if ((intel_panel_use_ssc(dev_priv) &&
                     dev_priv->vbt.lvds_ssc_freq == 100000) ||
-                   (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
+                   (HAS_PCH_IBX(dev_priv) &&
+                    intel_is_dual_link_lvds(dev_priv)))
                        factor = 25;
-       } else if (crtc_state->sdvo_tv_clock)
+       } else if (crtc_state->sdvo_tv_clock) {
                factor = 20;
+       }
 
        fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
 
@@ -8939,8 +8965,7 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
                                       struct intel_crtc_state *crtc_state)
 {
-       struct drm_device *dev = crtc->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        const struct intel_limit *limit;
        int refclk = 120000;
 
@@ -8958,7 +8983,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
                        refclk = dev_priv->vbt.lvds_ssc_freq;
                }
 
-               if (intel_is_dual_link_lvds(dev)) {
+               if (intel_is_dual_link_lvds(dev_priv)) {
                        if (refclk == 100000)
                                limit = &intel_limits_ironlake_dual_lvds_100m;
                        else
@@ -8982,7 +9007,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
 
        ironlake_compute_dpll(crtc, crtc_state, NULL);
 
-       if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
+       if (!intel_get_shared_dpll(crtc_state, NULL)) {
                DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
                              pipe_name(crtc->pipe));
                return -EINVAL;
@@ -9583,7 +9608,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
                struct intel_encoder *encoder =
                        intel_get_crtc_new_encoder(state, crtc_state);
 
-               if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
+               if (!intel_get_shared_dpll(crtc_state, encoder)) {
                        DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
                                      pipe_name(crtc->pipe));
                        return -EINVAL;