drm/i915/hsw, bdw: Add an ID for the global display power well

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c8647cfa81baab5c88f5d5c592814b1086a8816c..23dc1b5328d0615a5298fd6d702abda1a3075108 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1063,9 +1063,26 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   DP_SSS_RESET(pipe)                   _DP_SSS(0x2, (pipe))
 #define   DP_SSS_PWR_GATE(pipe)                        _DP_SSS(0x3, (pipe))
 
-/* See the PUNIT HAS v0.8 for the below bits */
-enum punit_power_well {
-       /* These numbers are fixed and must match the position of the pw bits */
+/**
+ * i915_power_well_id:
+ *
+ * Platform specific IDs used to look up power wells and - except for custom
+ * power wells - to define request/status register flag bit positions. As such
+ * the set of IDs on a given platform must be unique and except for custom
+ * power wells their value must stay fixed.
+ */
+enum i915_power_well_id {
+       /*
+        * I830
+        *  - custom power well
+        */
+       I830_DISP_PW_PIPES = 0,
+
+       /*
+        * VLV/CHV
+        *  - PUNIT_REG_PWRGT_CTRL (bit: id*2),
+        *    PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8)
+        */
        PUNIT_POWER_WELL_RENDER                 = 0,
        PUNIT_POWER_WELL_MEDIA                  = 1,
        PUNIT_POWER_WELL_DISP2D                 = 3,
@@ -1077,14 +1094,20 @@ enum punit_power_well {
        PUNIT_POWER_WELL_DPIO_RX0               = 10,
        PUNIT_POWER_WELL_DPIO_RX1               = 11,
        PUNIT_POWER_WELL_DPIO_CMN_D             = 12,
-
-       /* Not actual bit groups. Used as IDs for lookup_power_well() */
-       PUNIT_POWER_WELL_ALWAYS_ON,
-};
-
-enum skl_disp_power_wells {
-       /* These numbers are fixed and must match the position of the pw bits */
-       SKL_DISP_PW_MISC_IO,
+       /*  - custom power well */
+       CHV_DISP_PW_PIPE_A,                     /* 13 */
+
+       /*
+        * HSW/BDW
+        *  - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1)
+        */
+       HSW_DISP_PW_GLOBAL = 15,
+
+       /*
+        * GEN9+
+        *  - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1)
+        */
+       SKL_DISP_PW_MISC_IO = 0,
        SKL_DISP_PW_DDI_A_E,
        GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
        CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
@@ -1103,13 +1126,18 @@ enum skl_disp_power_wells {
        SKL_DISP_PW_1 = 14,
        SKL_DISP_PW_2,
 
-       /* Not actual bit groups. Used as IDs for lookup_power_well() */
-       SKL_DISP_PW_ALWAYS_ON,
+       /* - custom power wells */
        SKL_DISP_PW_DC_OFF,
-
        BXT_DPIO_CMN_A,
        BXT_DPIO_CMN_BC,
-       GLK_DPIO_CMN_C,
+       GLK_DPIO_CMN_C,                 /* 19 */
+
+       /*
+        * Multiple platforms.
+        * Must start following the highest ID of any platform.
+        * - custom power wells
+        */
+       I915_DISP_PW_ALWAYS_ON = 20,
 };
 
 #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
@@ -1802,7 +1830,7 @@ enum skl_disp_power_wells {
 #define   POST_CURSOR_2(x)             ((x) << 6)
 #define   POST_CURSOR_2_MASK           (0x3F << 6)
 #define   CURSOR_COEFF(x)              ((x) << 0)
-#define   CURSOR_COEFF_MASK            (0x3F << 6)
+#define   CURSOR_COEFF_MASK            (0x3F << 0)
 
 #define _CNL_PORT_TX_DW5_GRP_AE                0x162354
 #define _CNL_PORT_TX_DW5_GRP_B         0x1623D4
@@ -3522,7 +3550,7 @@ enum skl_disp_power_wells {
 #define INTERVAL_1_28_US(us)   roundup(((us) * 100) >> 7, 25)
 #define INTERVAL_1_33_US(us)   (((us) * 3)   >> 2)
 #define INTERVAL_0_833_US(us)  (((us) * 6) / 5)
-#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
+#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
                                (IS_GEN9_LP(dev_priv) ? \
                                INTERVAL_0_833_US(us) : \
                                INTERVAL_1_33_US(us)) : \
@@ -3531,7 +3559,7 @@ enum skl_disp_power_wells {
 #define INTERVAL_1_28_TO_US(interval)  (((interval) << 7) / 100)
 #define INTERVAL_1_33_TO_US(interval)  (((interval) << 2) / 3)
 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5)  / 6)
-#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
+#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
                            (IS_GEN9_LP(dev_priv) ? \
                            INTERVAL_0_833_TO_US(interval) : \
                            INTERVAL_1_33_TO_US(interval)) : \
@@ -8343,6 +8371,7 @@ enum {
 #define  DPLL_CFGCR0_LINK_RATE_3240    (6 << 25)
 #define  DPLL_CFGCR0_LINK_RATE_4050    (7 << 25)
 #define  DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
+#define  DPLL_CFGCR0_DCO_FRAC_SHIFT    (10)
 #define  DPLL_CFGCR0_DCO_FRACTION(x)   ((x) << 10)
 #define  DPLL_CFGCR0_DCO_INTEGER_MASK  (0x3ff)
 #define CNL_DPLL_CFGCR0(pll)           _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
@@ -8350,6 +8379,7 @@ enum {
 #define _CNL_DPLL0_CFGCR1              0x6C004
 #define _CNL_DPLL1_CFGCR1              0x6C084
 #define  DPLL_CFGCR1_QDIV_RATIO_MASK   (0xff << 10)
+#define  DPLL_CFGCR1_QDIV_RATIO_SHIFT  (10)
 #define  DPLL_CFGCR1_QDIV_RATIO(x)     ((x) << 10)
 #define  DPLL_CFGCR1_QDIV_MODE(x)      ((x) << 9)
 #define  DPLL_CFGCR1_KDIV_MASK         (7 << 6)