Merge tag 'drm-intel-next-fixes-2017-04-27' of git://anongit.freedesktop.org/git...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_drv.c
index 7b4fa84cbc3ce3918692b9e68b2b651e87d8ba6a..3036d4835b0fa7a3b366a31d0b6ed18fc7889ae1 100644 (file)
@@ -2175,6 +2175,20 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
        I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
 }
 
+static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
+                                 u32 mask, u32 val)
+{
+       /* The HW does not like us polling for PW_STATUS frequently, so
+        * use the sleeping loop rather than risk the busy spin within
+        * intel_wait_for_register().
+        *
+        * Transitioning between RC6 states should be at most 2ms (see
+        * valleyview_enable_rps) so use a 3ms timeout.
+        */
+       return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
+                       3);
+}
+
 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
 {
        u32 val;
@@ -2203,8 +2217,9 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
 
 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
 {
+       u32 mask;
        u32 val;
-       int err = 0;
+       int err;
 
        val = I915_READ(VLV_GTLC_WAKE_CTRL);
        val &= ~VLV_GTLC_ALLOWWAKEREQ;
@@ -2213,45 +2228,32 @@ static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
        I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
        POSTING_READ(VLV_GTLC_WAKE_CTRL);
 
-       err = intel_wait_for_register(dev_priv,
-                                     VLV_GTLC_PW_STATUS,
-                                     VLV_GTLC_ALLOWWAKEACK,
-                                     allow,
-                                     1);
+       mask = VLV_GTLC_ALLOWWAKEACK;
+       val = allow ? mask : 0;
+
+       err = vlv_wait_for_pw_status(dev_priv, mask, val);
        if (err)
                DRM_ERROR("timeout disabling GT waking\n");
 
        return err;
 }
 
-static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
-                                bool wait_for_on)
+static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
+                                 bool wait_for_on)
 {
        u32 mask;
        u32 val;
-       int err;
 
        mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
        val = wait_for_on ? mask : 0;
-       if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
-               return 0;
-
-       DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
-                     onoff(wait_for_on),
-                     I915_READ(VLV_GTLC_PW_STATUS));
 
        /*
         * RC6 transitioning can be delayed up to 2 msec (see
         * valleyview_enable_rps), use 3 msec for safety.
         */
-       err = intel_wait_for_register(dev_priv,
-                                     VLV_GTLC_PW_STATUS, mask, val,
-                                     3);
-       if (err)
+       if (vlv_wait_for_pw_status(dev_priv, mask, val))
                DRM_ERROR("timeout waiting for GT wells to go %s\n",
                          onoff(wait_for_on));
-
-       return err;
 }
 
 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
@@ -2272,7 +2274,7 @@ static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
         * Bspec defines the following GT well on flags as debug only, so
         * don't treat them as hard failures.
         */
-       (void)vlv_wait_for_gt_wells(dev_priv, false);
+       vlv_wait_for_gt_wells(dev_priv, false);
 
        mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
        WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);