drm/i915/gvt: cancel virtual vblank timer when no vGPU exists

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / gvt / vgpu.c

diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 02c61a1ad56a213146f808eb506ac00dccc257d3..a8784fa91289c82d442f6b90cb13fb4f837fe7b3 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -38,22 +38,25 @@
 void populate_pvinfo_page(struct intel_vgpu *vgpu)
 {
        /* setup the ballooning information */
-       vgpu_vreg64(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
-       vgpu_vreg(vgpu, vgtif_reg(version_major)) = 1;
-       vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0;
-       vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0;
-       vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
-       vgpu_vreg(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
-       vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
+       vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
+       vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
+       vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
+       vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
+       vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
+
+       vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
+       vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
+
+       vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
                vgpu_aperture_gmadr_base(vgpu);
-       vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
+       vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
                vgpu_aperture_sz(vgpu);
-       vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
+       vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
                vgpu_hidden_gmadr_base(vgpu);
-       vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
+       vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
                vgpu_hidden_sz(vgpu);
 
-       vgpu_vreg(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
+       vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
 
        gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
        gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
@@ -226,13 +229,14 @@ void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
 
        vgpu->active = false;
 
-       if (atomic_read(&vgpu->running_workload_num)) {
+       if (atomic_read(&vgpu->submission.running_workload_num)) {
                mutex_unlock(&gvt->lock);
                intel_gvt_wait_vgpu_idle(vgpu);
                mutex_lock(&gvt->lock);
        }
 
        intel_vgpu_stop_schedule(vgpu);
+       intel_vgpu_dmabuf_cleanup(vgpu);
 
        mutex_unlock(&gvt->lock);
 }
@@ -252,16 +256,19 @@ void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
 
        WARN(vgpu->active, "vGPU is still active!\n");
 
+       intel_gvt_debugfs_remove_vgpu(vgpu);
        idr_remove(&gvt->vgpu_idr, vgpu->id);
+       if (idr_is_empty(&gvt->vgpu_idr))
+               intel_gvt_clean_irq(gvt);
        intel_vgpu_clean_sched_policy(vgpu);
-       intel_vgpu_clean_gvt_context(vgpu);
-       intel_vgpu_clean_execlist(vgpu);
+       intel_vgpu_clean_submission(vgpu);
        intel_vgpu_clean_display(vgpu);
        intel_vgpu_clean_opregion(vgpu);
        intel_vgpu_clean_gtt(vgpu);
        intel_gvt_hypervisor_detach_vgpu(vgpu);
        intel_vgpu_free_resource(vgpu);
        intel_vgpu_clean_mmio(vgpu);
+       intel_vgpu_dmabuf_cleanup(vgpu);
        vfree(vgpu);
 
        intel_gvt_update_vgpu_types(gvt);
@@ -293,7 +300,7 @@ struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt)
        vgpu->gvt = gvt;
 
        for (i = 0; i < I915_NUM_ENGINES; i++)
-               INIT_LIST_HEAD(&vgpu->workload_q_head[i]);
+               INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]);
 
        ret = intel_vgpu_init_sched_policy(vgpu);
        if (ret)
@@ -346,8 +353,8 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
        vgpu->handle = param->handle;
        vgpu->gvt = gvt;
        vgpu->sched_ctl.weight = param->weight;
-       bitmap_zero(vgpu->tlb_handle_pending, I915_NUM_ENGINES);
-
+       INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head);
+       idr_init(&vgpu->object_idr);
        intel_vgpu_init_cfg_space(vgpu, param->primary);
 
        ret = intel_vgpu_init_mmio(vgpu);
@@ -368,32 +375,42 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
        if (ret)
                goto out_detach_hypervisor_vgpu;
 
-       ret = intel_vgpu_init_display(vgpu, param->resolution);
+       ret = intel_vgpu_init_opregion(vgpu);
        if (ret)
                goto out_clean_gtt;
 
-       ret = intel_vgpu_init_execlist(vgpu);
+       ret = intel_vgpu_init_display(vgpu, param->resolution);
        if (ret)
-               goto out_clean_display;
+               goto out_clean_opregion;
 
-       ret = intel_vgpu_init_gvt_context(vgpu);
+       ret = intel_vgpu_setup_submission(vgpu);
        if (ret)
-               goto out_clean_execlist;
+               goto out_clean_display;
 
        ret = intel_vgpu_init_sched_policy(vgpu);
        if (ret)
-               goto out_clean_shadow_ctx;
+               goto out_clean_submission;
+
+       ret = intel_gvt_debugfs_add_vgpu(vgpu);
+       if (ret)
+               goto out_clean_sched_policy;
+
+       ret = intel_gvt_hypervisor_set_opregion(vgpu);
+       if (ret)
+               goto out_clean_sched_policy;
 
        mutex_unlock(&gvt->lock);
 
        return vgpu;
 
-out_clean_shadow_ctx:
-       intel_vgpu_clean_gvt_context(vgpu);
-out_clean_execlist:
-       intel_vgpu_clean_execlist(vgpu);
+out_clean_sched_policy:
+       intel_vgpu_clean_sched_policy(vgpu);
+out_clean_submission:
+       intel_vgpu_clean_submission(vgpu);
 out_clean_display:
        intel_vgpu_clean_display(vgpu);
+out_clean_opregion:
+       intel_vgpu_clean_opregion(vgpu);
 out_clean_gtt:
        intel_vgpu_clean_gtt(vgpu);
 out_detach_hypervisor_vgpu:
@@ -500,10 +517,10 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
                mutex_lock(&gvt->lock);
        }
 
-       intel_vgpu_reset_execlist(vgpu, resetting_eng);
-
+       intel_vgpu_reset_submission(vgpu, resetting_eng);
        /* full GPU reset or device model level reset */
        if (engine_mask == ALL_ENGINES || dmlr) {
+               intel_vgpu_select_submission_ops(vgpu, 0);
 
                /*fence will not be reset during virtual reset */
                if (dmlr) {