Merge tag 'gvt-next-2017-12-14' of https://github.com/intel/gvt-linux into drm-intel...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / gvt / handlers.c
index 94fc04210bac96ed27cbfe701867f1f5a1e6513d..c982867e7c2b11924df8539a96f57e12d1cb5c6e 100644 (file)
@@ -174,8 +174,10 @@ void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
                break;
        case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
                pr_err("Graphics resource is not enough for the guest\n");
+               break;
        case GVT_FAILSAFE_GUEST_ERR:
                pr_err("GVT Internal error  for the guest\n");
+               break;
        default:
                break;
        }
@@ -1396,7 +1398,7 @@ static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
         * update the VM CSB status correctly. Here listed registers can
         * support BDW, SKL or other platforms with same HWSP registers.
         */
-       if (unlikely(ring_id < 0 || ring_id > I915_NUM_ENGINES)) {
+       if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) {
                gvt_vgpu_err("VM(%d) access unknown hardware status page register:0x%x\n",
                             vgpu->id, offset);
                return -EINVAL;
@@ -1471,7 +1473,7 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
        u32 data = *(u32 *)p_data;
        int ret = 0;
 
-       if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1))
+       if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
                return -EINVAL;
 
        execlist = &vgpu->submission.execlist[ring_id];