Merge tag 'gvt-next-2017-12-14' of https://github.com/intel/gvt-linux into drm-intel...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / gvt / gvt.h

diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 9c2e7c0aa38fb68670a26789d4efcf58aa42b607..1e9f11c8b7bbf432170b90a41b15d3133a9d6e21 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -44,8 +44,10 @@
 #include "execlist.h"
 #include "scheduler.h"
 #include "sched_policy.h"
-#include "render.h"
+#include "mmio_context.h"
 #include "cmd_parser.h"
+#include "fb_decoder.h"
+#include "dmabuf.h"
 
 #define GVT_MAX_VGPU 8
 
@@ -123,9 +125,10 @@ struct intel_vgpu_irq {
 };
 
 struct intel_vgpu_opregion {
+       bool mapped;
        void *va;
+       void *va_gopregion;
        u32 gfn[INTEL_GVT_OPREGION_PAGES];
-       struct page *pages[INTEL_GVT_OPREGION_PAGES];
 };
 
 #define vgpu_opregion(vgpu) (&(vgpu->opregion))
@@ -142,6 +145,33 @@ struct vgpu_sched_ctl {
        int weight;
 };
 
+enum {
+       INTEL_VGPU_EXECLIST_SUBMISSION = 1,
+       INTEL_VGPU_GUC_SUBMISSION,
+};
+
+struct intel_vgpu_submission_ops {
+       const char *name;
+       int (*init)(struct intel_vgpu *vgpu);
+       void (*clean)(struct intel_vgpu *vgpu);
+       void (*reset)(struct intel_vgpu *vgpu, unsigned long engine_mask);
+};
+
+struct intel_vgpu_submission {
+       struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
+       struct list_head workload_q_head[I915_NUM_ENGINES];
+       struct kmem_cache *workloads;
+       atomic_t running_workload_num;
+       struct i915_gem_context *shadow_ctx;
+       DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
+       DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
+       void *ring_scan_buffer[I915_NUM_ENGINES];
+       int ring_scan_buffer_size[I915_NUM_ENGINES];
+       const struct intel_vgpu_submission_ops *ops;
+       int virtual_submission_interface;
+       bool active;
+};
+
 struct intel_vgpu {
        struct intel_gvt *gvt;
        int id;
@@ -161,16 +191,10 @@ struct intel_vgpu {
        struct intel_vgpu_gtt gtt;
        struct intel_vgpu_opregion opregion;
        struct intel_vgpu_display display;
-       struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
-       struct list_head workload_q_head[I915_NUM_ENGINES];
-       struct kmem_cache *workloads;
-       atomic_t running_workload_num;
-       /* 1/2K for each reserve ring buffer */
-       void *reserve_ring_buffer_va[I915_NUM_ENGINES];
-       int reserve_ring_buffer_size[I915_NUM_ENGINES];
-       DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
-       struct i915_gem_context *shadow_ctx;
-       DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
+       struct intel_vgpu_submission submission;
+       u32 hws_pga[I915_NUM_ENGINES];
+
+       struct dentry *debugfs;
 
 #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT)
        struct {
@@ -186,10 +210,22 @@ struct intel_vgpu {
                struct kvm *kvm;
                struct work_struct release_work;
                atomic_t released;
+               struct vfio_device *vfio_device;
        } vdev;
 #endif
+
+       struct list_head dmabuf_obj_list_head;
+       struct mutex dmabuf_lock;
+       struct idr object_idr;
+
+       struct completion vblank_done;
+
 };
 
+/* validating GM healthy status*/
+#define vgpu_is_vm_unhealthy(ret_val) \
+       (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT))
+
 struct intel_gvt_gm {
        unsigned long vgpu_allocated_low_gm_size;
        unsigned long vgpu_allocated_high_gm_size;
@@ -231,7 +267,7 @@ struct intel_gvt_mmio {
        unsigned int num_mmio_block;
 
        DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
-       unsigned int num_tracked_mmio;
+       unsigned long num_tracked_mmio;
 };
 
 struct intel_gvt_firmware {
@@ -240,11 +276,6 @@ struct intel_gvt_firmware {
        bool firmware_loaded;
 };
 
-struct intel_gvt_opregion {
-       void *opregion_va;
-       u32 opregion_pa;
-};
-
 #define NR_MAX_INTEL_VGPU_TYPES 20
 struct intel_vgpu_type {
        char name[16];
@@ -268,7 +299,6 @@ struct intel_gvt {
        struct intel_gvt_firmware firmware;
        struct intel_gvt_irq irq;
        struct intel_gvt_gtt gtt;
-       struct intel_gvt_opregion opregion;
        struct intel_gvt_workload_scheduler scheduler;
        struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
        DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS);
@@ -279,6 +309,10 @@ struct intel_gvt {
        struct task_struct *service_thread;
        wait_queue_head_t service_thread_wq;
        unsigned long service_request;
+
+       struct engine_mmio *engine_mmio_list;
+
+       struct dentry *debugfs_root;
 };
 
 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915)
@@ -316,7 +350,7 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt);
 
 /* Aperture/GM space definitions for GVT device */
 #define gvt_aperture_sz(gvt)     (gvt->dev_priv->ggtt.mappable_end)
-#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)
+#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.gmadr.start)
 
 #define gvt_ggtt_gm_sz(gvt)      (gvt->dev_priv->ggtt.base.total)
 #define gvt_ggtt_sz(gvt) \
@@ -484,16 +518,15 @@ static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)
                        PCI_BASE_ADDRESS_MEM_MASK;
 }
 
-void intel_gvt_clean_opregion(struct intel_gvt *gvt);
-int intel_gvt_init_opregion(struct intel_gvt *gvt);
-
 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
-int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa);
+int intel_vgpu_init_opregion(struct intel_vgpu *vgpu);
+int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa);
 
 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);
 void populate_pvinfo_page(struct intel_vgpu *vgpu);
 
 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload);
+void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason);
 
 struct intel_gvt_ops {
        int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *,
@@ -510,12 +543,19 @@ struct intel_gvt_ops {
        void (*vgpu_reset)(struct intel_vgpu *);
        void (*vgpu_activate)(struct intel_vgpu *);
        void (*vgpu_deactivate)(struct intel_vgpu *);
+       struct intel_vgpu_type *(*gvt_find_vgpu_type)(struct intel_gvt *gvt,
+                       const char *name);
+       bool (*get_gvt_attrs)(struct attribute ***type_attrs,
+                       struct attribute_group ***intel_vgpu_type_groups);
+       int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *);
+       int (*vgpu_get_dmabuf)(struct intel_vgpu *vgpu, unsigned int);
 };
 
 
 enum {
        GVT_FAILSAFE_UNSUPPORTED_GUEST,
        GVT_FAILSAFE_INSUFFICIENT_RESOURCE,
+       GVT_FAILSAFE_GUEST_ERR,
 };
 
 static inline void mmio_hw_access_pre(struct drm_i915_private *dev_priv)
@@ -591,6 +631,12 @@ static inline bool intel_gvt_mmio_has_mode_mask(
        return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK;
 }
 
+int intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
+void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);
+int intel_gvt_debugfs_init(struct intel_gvt *gvt);
+void intel_gvt_debugfs_clean(struct intel_gvt *gvt);
+
+
 #include "trace.h"
 #include "mpt.h"