Merge drm/drm-next into drm-intel-next-queued
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / gt / intel_workarounds.c
index 15e90fd2cfdc2e9882cfeff9f2e2e1e4a1ff1a7e..f6fd6905ee6fb4758f93287dcfb3e436a915adea 100644 (file)
@@ -6,6 +6,7 @@
 
 #include "i915_drv.h"
 #include "intel_context.h"
+#include "intel_gt.h"
 #include "intel_workarounds.h"
 
 /**
@@ -990,9 +991,9 @@ wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
        spin_unlock_irqrestore(&uncore->lock, flags);
 }
 
-void intel_gt_apply_workarounds(struct drm_i915_private *i915)
+void intel_gt_apply_workarounds(struct intel_gt *gt)
 {
-       wa_list_apply(&i915->uncore, &i915->gt_wa_list);
+       wa_list_apply(gt->uncore, &gt->i915->gt_wa_list);
 }
 
 static bool wa_list_verify(struct intel_uncore *uncore,
@@ -1011,10 +1012,9 @@ static bool wa_list_verify(struct intel_uncore *uncore,
        return ok;
 }
 
-bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
-                                const char *from)
+bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
 {
-       return wa_list_verify(&i915->uncore, &i915->gt_wa_list, from);
+       return wa_list_verify(gt->uncore, &gt->i915->gt_wa_list, from);
 }
 
 static void
@@ -1098,10 +1098,25 @@ static void glk_whitelist_build(struct intel_engine_cs *engine)
 
 static void cfl_whitelist_build(struct intel_engine_cs *engine)
 {
+       struct i915_wa_list *w = &engine->whitelist;
+
        if (engine->class != RENDER_CLASS)
                return;
 
-       gen9_whitelist_build(&engine->whitelist);
+       gen9_whitelist_build(w);
+
+       /*
+        * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
+        *
+        * This covers 4 register which are next to one another :
+        *   - PS_INVOCATION_COUNT
+        *   - PS_INVOCATION_COUNT_UDW
+        *   - PS_DEPTH_COUNT
+        *   - PS_DEPTH_COUNT_UDW
+        */
+       whitelist_reg_ext(w, PS_INVOCATION_COUNT,
+                         RING_FORCE_TO_NONPRIV_RD |
+                         RING_FORCE_TO_NONPRIV_RANGE_4);
 }
 
 static void cnl_whitelist_build(struct intel_engine_cs *engine)
@@ -1129,6 +1144,19 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
 
                /* WaEnableStateCacheRedirectToCS:icl */
                whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
+
+               /*
+                * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
+                *
+                * This covers 4 register which are next to one another :
+                *   - PS_INVOCATION_COUNT
+                *   - PS_INVOCATION_COUNT_UDW
+                *   - PS_DEPTH_COUNT
+                *   - PS_DEPTH_COUNT_UDW
+                */
+               whitelist_reg_ext(w, PS_INVOCATION_COUNT,
+                                 RING_FORCE_TO_NONPRIV_RD |
+                                 RING_FORCE_TO_NONPRIV_RANGE_4);
                break;
 
        case VIDEO_DECODE_CLASS:
@@ -1258,8 +1286,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
                        wa_write_or(wal,
                                    GEN7_SARCHKMD,
-                                   GEN7_DISABLE_DEMAND_PREFETCH |
-                                   GEN7_DISABLE_SAMPLER_PREFETCH);
+                                   GEN7_DISABLE_DEMAND_PREFETCH);
+
+               /* Wa_1606682166:icl */
+               wa_write_or(wal,
+                           GEN7_SARCHKMD,
+                           GEN7_DISABLE_SAMPLER_PREFETCH);
        }
 
        if (IS_GEN_RANGE(i915, 9, 11)) {
@@ -1328,7 +1360,7 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal
        if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 8))
                return;
 
-       if (engine->id == RCS0)
+       if (engine->class == RENDER_CLASS)
                rcs_engine_wa_init(engine, wal);
        else
                xcs_engine_wa_init(engine, wal);
@@ -1338,7 +1370,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
 {
        struct i915_wa_list *wal = &engine->wa_list;
 
-       if (GEM_WARN_ON(INTEL_GEN(engine->i915) < 8))
+       if (INTEL_GEN(engine->i915) < 8)
                return;
 
        wa_init_start(wal, engine->name);
@@ -1426,7 +1458,7 @@ static int engine_wa_list_verify(struct intel_context *ce,
        if (!wal->count)
                return 0;
 
-       vma = create_scratch(&ce->engine->i915->ggtt.vm, wal->count);
+       vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count);
        if (IS_ERR(vma))
                return PTR_ERR(vma);