drm/amd/display: fix a couple of spelling mistakes
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / display / dc / dsc / dc_dsc.c
index 77e7a0f8a527e3d3450db6f2def4096ffb0d7f2c..ef5f84a144c35d7ad449a9b173367929ce9fdf2e 100644 (file)
@@ -47,7 +47,7 @@ static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_bl
                *buff_block_size = 64 * 1024;
                break;
        default: {
-                       dm_error("%s: DPCD DSC buffer size not recoginzed.\n", __func__);
+                       dm_error("%s: DPCD DSC buffer size not recognized.\n", __func__);
                        return false;
                }
        }
@@ -63,7 +63,7 @@ static bool dsc_line_buff_depth_from_dpcd(int dpcd_line_buff_bit_depth, int *lin
        else if (dpcd_line_buff_bit_depth == 8)
                *line_buff_bit_depth = 8;
        else {
-               dm_error("%s: DPCD DSC buffer depth not recoginzed.\n", __func__);
+               dm_error("%s: DPCD DSC buffer depth not recognized.\n", __func__);
                return false;
        }
 
@@ -123,7 +123,7 @@ static bool dsc_throughput_from_dpcd(int dpcd_throughput, int *throughput)
                *throughput = 1000;
                break;
        default: {
-                       dm_error("%s: DPCD DSC througput mode not recoginzed.\n", __func__);
+                       dm_error("%s: DPCD DSC throughput mode not recognized.\n", __func__);
                        return false;
                }
        }
@@ -152,7 +152,7 @@ static bool dsc_bpp_increment_div_from_dpcd(int bpp_increment_dpcd, uint32_t *bp
                *bpp_increment_div = 1;
                break;
        default: {
-               dm_error("%s: DPCD DSC bits-per-pixel increment not recoginzed.\n", __func__);
+               dm_error("%s: DPCD DSC bits-per-pixel increment not recognized.\n", __func__);
                return false;
        }
        }