Merge branch 'drm-next-5.2' of git://people.freedesktop.org/~agd5f/linux into drm...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / display / dc / calcs / dcn_calcs.c

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index eb62d10bb65cd75843a2e385b7ff9f348a266b13..1e23ddc7d088edb1561c92b2c1da7ca8fed20d01 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -247,6 +247,53 @@ static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format for
        }
 }
 
+enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode)
+{
+       switch (sw_mode) {
+       /* for 4/8/16 high tiles */
+       case DC_SW_LINEAR:
+               return dm_4k_tile;
+       case DC_SW_4KB_S:
+       case DC_SW_4KB_S_X:
+               return dm_4k_tile;
+       case DC_SW_64KB_S:
+       case DC_SW_64KB_S_X:
+       case DC_SW_64KB_S_T:
+               return dm_64k_tile;
+       case DC_SW_VAR_S:
+       case DC_SW_VAR_S_X:
+               return dm_256k_tile;
+
+       /* For 64bpp 2 high tiles */
+       case DC_SW_4KB_D:
+       case DC_SW_4KB_D_X:
+               return dm_4k_tile;
+       case DC_SW_64KB_D:
+       case DC_SW_64KB_D_X:
+       case DC_SW_64KB_D_T:
+               return dm_64k_tile;
+       case DC_SW_VAR_D:
+       case DC_SW_VAR_D_X:
+               return dm_256k_tile;
+
+       case DC_SW_4KB_R:
+       case DC_SW_4KB_R_X:
+               return dm_4k_tile;
+       case DC_SW_64KB_R:
+       case DC_SW_64KB_R_X:
+               return dm_64k_tile;
+       case DC_SW_VAR_R:
+       case DC_SW_VAR_R_X:
+               return dm_256k_tile;
+
+       /* Unsupported swizzle modes for dcn */
+       case DC_SW_256B_S:
+       default:
+               ASSERT(0); /* Not supported */
+               return 0;
+       }
+}
+
 static void pipe_ctx_to_e2e_pipe_params (
                const struct pipe_ctx *pipe,
                struct _vcs_dpi_display_pipe_params_st *input)
@@ -287,46 +334,7 @@ static void pipe_ctx_to_e2e_pipe_params (
        input->src.cur0_src_width      = 128; /* TODO: Cursor calcs, not curently stored */
        input->src.cur0_bpp            = 32;
 
-       switch (pipe->plane_state->tiling_info.gfx9.swizzle) {
-       /* for 4/8/16 high tiles */
-       case DC_SW_LINEAR:
-               input->src.macro_tile_size = dm_4k_tile;
-               break;
-       case DC_SW_4KB_S:
-       case DC_SW_4KB_S_X:
-               input->src.macro_tile_size = dm_4k_tile;
-               break;
-       case DC_SW_64KB_S:
-       case DC_SW_64KB_S_X:
-       case DC_SW_64KB_S_T:
-               input->src.macro_tile_size = dm_64k_tile;
-               break;
-       case DC_SW_VAR_S:
-       case DC_SW_VAR_S_X:
-               input->src.macro_tile_size = dm_256k_tile;
-               break;
-
-       /* For 64bpp 2 high tiles */
-       case DC_SW_4KB_D:
-       case DC_SW_4KB_D_X:
-               input->src.macro_tile_size = dm_4k_tile;
-               break;
-       case DC_SW_64KB_D:
-       case DC_SW_64KB_D_X:
-       case DC_SW_64KB_D_T:
-               input->src.macro_tile_size = dm_64k_tile;
-               break;
-       case DC_SW_VAR_D:
-       case DC_SW_VAR_D_X:
-               input->src.macro_tile_size = dm_256k_tile;
-               break;
-
-       /* Unsupported swizzle modes for dcn */
-       case DC_SW_256B_S:
-       default:
-               ASSERT(0); /* Not supported */
-               break;
-       }
+       input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);
 
        switch (pipe->plane_state->rotation) {
        case ROTATION_ANGLE_0:
@@ -466,7 +474,7 @@ static void dcn_bw_calc_rq_dlg_ttu(
        input.clks_cfg.dcfclk_mhz = v->dcfclk;
        input.clks_cfg.dispclk_mhz = v->dispclk;
        input.clks_cfg.dppclk_mhz = v->dppclk;
-       input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz / 1000.0;
+       input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
        input.clks_cfg.socclk_mhz = v->socclk;
        input.clks_cfg.voltage = v->voltage_level;
 //     dc->dml.logger = pool->base.logger;
@@ -1141,7 +1149,7 @@ bool dcn_validate_bandwidth(
                                                hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
                                        } else {
                                                /* pipe not split previously needs split */
-                                               hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool);
+                                               hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool, pipe);
                                                ASSERT(hsplit_pipe);
                                                split_stream_across_pipes(
                                                        &context->res_ctx, pool,
@@ -1395,12 +1403,14 @@ void dcn_bw_update_from_pplib(struct dc *dc)
 
 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
 {
-       struct pp_smu_funcs_rv *pp = dc->res_pool->pp_smu;
+       struct pp_smu_funcs_rv *pp = NULL;
        struct pp_smu_wm_range_sets ranges = {0};
        int min_fclk_khz, min_dcfclk_khz, socclk_khz;
        const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
 
-       if (!pp->set_wm_ranges)
+       if (dc->res_pool->pp_smu)
+               pp = &dc->res_pool->pp_smu->rv_funcs;
+       if (!pp || !pp->set_wm_ranges)
                return;
 
        kernel_fpu_begin();