drm/amd/powerplay: no memory activity support on Vega10

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / vcn_v1_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index d30ff256ff575d16258425cab701745a4aac6797..dde22b7d140dfe458fbedfcea837b6c208a0fcfc 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -128,6 +128,17 @@ static int vcn_v1_0_sw_init(void *handle)
        if (r)
                return r;
 
+       adev->vcn.internal.scratch9 = adev->vcn.external.scratch9 =
+               SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
+       adev->vcn.internal.data0 = adev->vcn.external.data0 =
+               SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
+       adev->vcn.internal.data1 = adev->vcn.external.data1 =
+               SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
+       adev->vcn.internal.cmd = adev->vcn.external.cmd =
+               SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
+       adev->vcn.internal.nop = adev->vcn.external.nop =
+               SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
+
        for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
                ring = &adev->vcn.ring_enc[i];
                sprintf(ring->name, "vcn_enc%d", i);
@@ -143,6 +154,8 @@ static int vcn_v1_0_sw_init(void *handle)
                return r;
 
        adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
+       adev->vcn.internal.jpeg_pitch = adev->vcn.external.jpeg_pitch =
+               SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
 
        return 0;
 }