drm/amdgpu/vcn:Update DPG mode VCN memory control

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / vcn_v1_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index e597116d8282fab73935d53e622491c08de25096..0f3597c221c767f948a4ad7c945584ddaa0f7009 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -983,11 +983,13 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
 
        /* initialize VCN memory controller */
        WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
-               (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
+               (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
                UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
                UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
                UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
                UVD_LMI_CTRL__REQ_MODE_MASK |
+               UVD_LMI_CTRL__CRC_RESET_MASK |
+               UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
                0x00100000L, 0xFFFFFFFF, 0);
 
 #ifdef __BIG_ENDIAN
@@ -1041,13 +1043,14 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
        vcn_v1_0_clock_gating_dpg_mode(adev, 1);
        /* setup mmUVD_LMI_CTRL */
        WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
-                       (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
-                               UVD_LMI_CTRL__CRC_RESET_MASK |
-                               UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
-                               UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
-                               UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
-                               (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
-                               0x00100000L), 0xFFFFFFFF, 1);
+               (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
+               UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+               UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+               UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
+               UVD_LMI_CTRL__REQ_MODE_MASK |
+               UVD_LMI_CTRL__CRC_RESET_MASK |
+               UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+               0x00100000L, 0xFFFFFFFF, 1);
 
        tmp = adev->gfx.config.gb_addr_config;
        /* setup VCN global tiling registers */