Merge tag 'drm-for-v4.15-amd-dc' of git://people.freedesktop.org/~airlied/linux

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / soc15.c

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index f2c3a49f73a0051b74c602990d6e18ea64928eda..4e67fe1e79553d610c79819b525ecb881c13d059 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -101,7 +101,7 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 {
        unsigned long flags, address, data;
        u32 r;
-       struct nbio_pcie_index_data *nbio_pcie_id;
+       const struct nbio_pcie_index_data *nbio_pcie_id;
 
        if (adev->flags & AMD_IS_APU)
                nbio_pcie_id = &nbio_v7_0_pcie_index_data;
@@ -122,7 +122,7 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 {
        unsigned long flags, address, data;
-       struct nbio_pcie_index_data *nbio_pcie_id;
+       const struct nbio_pcie_index_data *nbio_pcie_id;
 
        if (adev->flags & AMD_IS_APU)
                nbio_pcie_id = &nbio_v7_0_pcie_index_data;
@@ -279,10 +279,7 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
 }
 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 {
-       if (adev->asic_type == CHIP_VEGA10)
-               return adev->clock.spll.reference_freq/4;
-       else
-               return adev->clock.spll.reference_freq;
+       return adev->clock.spll.reference_freq;
 }
 
 
@@ -407,18 +404,27 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
        return -EINVAL;
 }
 
-static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev)
+static int soc15_asic_reset(struct amdgpu_device *adev)
 {
        u32 i;
 
-       dev_info(adev->dev, "GPU pci config reset\n");
+       amdgpu_atombios_scratch_regs_engine_hung(adev, true);
+
+       dev_info(adev->dev, "GPU reset\n");
 
        /* disable BM */
        pci_clear_master(adev->pdev);
-       /* reset */
-       amdgpu_pci_config_reset(adev);
 
-       udelay(100);
+       pci_save_state(adev->pdev);
+
+       for (i = 0; i < AMDGPU_MAX_IP_NUM; i++) {
+               if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP){
+                       adev->ip_blocks[i].version->funcs->soft_reset((void *)adev);
+                       break;
+               }
+       }
+
+       pci_restore_state(adev->pdev);
 
        /* wait for asic to come out of reset */
        for (i = 0; i < adev->usec_timeout; i++) {
@@ -430,14 +436,6 @@ static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev)
                udelay(1);
        }
 
-}
-
-static int soc15_asic_reset(struct amdgpu_device *adev)
-{
-       amdgpu_atombios_scratch_regs_engine_hung(adev, true);
-
-       soc15_gpu_pci_config_reset(adev);
-
        amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 
        return 0;
@@ -534,6 +532,12 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
                        amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
                if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
                        amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC)
+               else if (amdgpu_device_has_dc_support(adev))
+                       amdgpu_ip_block_add(adev, &dm_ip_block);
+#else
+#      warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
+#endif
                amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
                amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
                amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block);
@@ -547,6 +551,12 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
                amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
                if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
                        amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC)
+               else if (amdgpu_device_has_dc_support(adev))
+                       amdgpu_ip_block_add(adev, &dm_ip_block);
+#else
+#      warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
+#endif
                amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
                amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
                amdgpu_ip_block_add(adev, &vcn_v1_0_ip_block);
@@ -603,21 +613,6 @@ static int soc15_common_early_init(void *handle)
                (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
                psp_enabled = true;
 
-       /*
-        * nbio need be used for both sdma and gfx9, but only
-        * initializes once
-        */
-       switch(adev->asic_type) {
-       case CHIP_VEGA10:
-               nbio_v6_1_init(adev);
-               break;
-       case CHIP_RAVEN:
-               nbio_v7_0_init(adev);
-               break;
-       default:
-               return -EINVAL;
-       }
-
        adev->rev_id = soc15_get_rev_id(adev);
        adev->external_rev_id = 0xFF;
        switch (adev->asic_type) {