Merge branch 'drm-next-5.2' of git://people.freedesktop.org/~agd5f/linux into drm...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / sdma_v4_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 058b9daec514005a4056b77dfb8595b44d57e566..8691b621148e6face6eeba7cd3e0c6b9a7295ddc 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -130,7 +130,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
 
 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
 {
-       SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
+       SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
        SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
        SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
        SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
@@ -160,7 +160,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
 };
 
 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
-       SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
+       SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
@@ -1522,6 +1522,10 @@ static int sdma_v4_0_late_init(void *handle)
                return 0;
        }
 
+       /* handle resume path. */
+       if (*ras_if)
+               goto resume;
+
        *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
        if (!*ras_if)
                return -ENOMEM;
@@ -1546,7 +1550,7 @@ static int sdma_v4_0_late_init(void *handle)
        r = amdgpu_ras_sysfs_create(adev, &fs_info);
        if (r)
                goto sysfs;
-
+resume:
        r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC0);
        if (r)
                goto irq;
@@ -1851,6 +1855,8 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
                return 0;
        }
 
+       kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+
        amdgpu_ras_reset_gpu(adev, 0);
 
        return AMDGPU_RAS_UE;
@@ -2259,8 +2265,8 @@ static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
 {
        adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
-       if (adev->sdma.has_page_queue)
-               adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
+       if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1)
+               adev->mman.buffer_funcs_ring = &adev->sdma.instance[1].page;
        else
                adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
 }
@@ -2279,15 +2285,21 @@ static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
        unsigned i;
 
        adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
-       for (i = 0; i < adev->sdma.num_instances; i++) {
-               if (adev->sdma.has_page_queue)
+       if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1) {
+               for (i = 1; i < adev->sdma.num_instances; i++) {
                        sched = &adev->sdma.instance[i].page.sched;
-               else
+                       adev->vm_manager.vm_pte_rqs[i - 1] =
+                               &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+               }
+               adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances - 1;
+       } else {
+               for (i = 0; i < adev->sdma.num_instances; i++) {
                        sched = &adev->sdma.instance[i].ring.sched;
-               adev->vm_manager.vm_pte_rqs[i] =
-                       &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+                       adev->vm_manager.vm_pte_rqs[i] =
+                               &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+               }
+               adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
        }
-       adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
 }
 
 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {