Merge tag 'v5.3-rc3' into drm-next-5.4

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / gfx_v7_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 21187275dfd37e496db7de2de3f21f2518a606f9..791ba398f007ef17e1330fd6160ba69d7f7d0043 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1890,6 +1890,24 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
        }
 }
 
+static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev)
+{
+       int vmid;
+
+       /*
+        * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
+        * access. Compute VMIDs should be enabled by FW for target VMIDs,
+        * the driver can enable them for graphics. VMID0 should maintain
+        * access so that HWS firmware can save/restore entries.
+        */
+       for (vmid = 1; vmid < 16; vmid++) {
+               WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
+       }
+}
+
 static void gfx_v7_0_config_init(struct amdgpu_device *adev)
 {
        adev->gfx.config.double_offchip_lds_buf = 1;
@@ -1968,6 +1986,7 @@ static void gfx_v7_0_constants_init(struct amdgpu_device *adev)
        mutex_unlock(&adev->srbm_mutex);
 
        gfx_v7_0_init_compute_vmid(adev);
+       gfx_v7_0_init_gds_vmid(adev);
 
        WREG32(mmSX_DEBUG_1, 0x20);