Merge tag 'v5.3-rc3' into drm-next-5.4
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / gfx_v10_0.c
index ec71e2a7d7b71c0af24f9e0a6f2818b3c5b06029..43427a3148b74094c6b89c7514b6148b97b86801 100644 (file)
@@ -1581,6 +1581,15 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
        }
        nv_grbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
+
+       /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+          acccess. These should be enabled by FW for target VMIDs. */
+       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
+       }
 }
 
 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
@@ -4778,6 +4787,7 @@ gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
                cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
                                            TIME_STAMP_INT_ENABLE, 0);
                WREG32(cp_int_cntl_reg, cp_int_cntl);
+               break;
        case AMDGPU_IRQ_STATE_ENABLE:
                cp_int_cntl = RREG32(cp_int_cntl_reg);
                cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,