#include <linux/dma-fence-array.h>
#include <linux/interval_tree_generic.h>
#include <linux/idr.h>
-#include <drm/drmP.h>
+
#include <drm/amdgpu_drm.h>
#include "amdgpu.h"
#include "amdgpu_trace.h"
flags &= ~AMDGPU_PTE_EXECUTABLE;
flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
- flags &= ~AMDGPU_PTE_MTYPE_MASK;
- flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
+ if (adev->asic_type == CHIP_NAVI10) {
+ flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
+ flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
+ } else {
+ flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
+ flags |= (mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK);
+ }
if ((mapping->flags & AMDGPU_PTE_PRT) &&
(adev->asic_type >= CHIP_VEGA10)) {
flags |= AMDGPU_PTE_PRT;
+ if (adev->asic_type >= CHIP_NAVI10) {
+ flags |= AMDGPU_PTE_SNOOPED;
+ flags |= AMDGPU_PTE_LOG;
+ flags |= AMDGPU_PTE_SYSTEM;
+ }
flags &= ~AMDGPU_PTE_VALID;
}