-/* Intel 7 core Memory Controller kernel module (Nehalem)
+/* Intel i7 core/Nehalem Memory Controller kernel module
+ *
+ * This driver supports yhe memory controllers found on the Intel
+ * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
+ * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
+ * and Westmere-EP.
*
* This file may be distributed under the terms of the
* GNU General Public License version 2 only.
*
- * Copyright (c) 2009 by:
+ * Copyright (c) 2009-2010 by:
* Mauro Carvalho Chehab <mchehab@redhat.com>
*
* Red Hat Inc. http://www.redhat.com
int optional;
};
+struct pci_id_table {
+ struct pci_id_descr *descr;
+ int n_devs;
+};
+
struct i7core_dev {
struct list_head list;
u8 socket;
.func = (function), \
.dev_id = (device_id)
-struct pci_id_descr pci_dev_descr_i7core[] = {
+struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
/* Memory controller */
{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
{ PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) },
};
+struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
+ /* Memory controller */
+ { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) },
+ { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) },
+ /* Exists only for RDIMM */
+ { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 },
+ { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },
+
+ /* Channel 0 */
+ { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
+ { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
+ { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
+ { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) },
+
+ /* Channel 1 */
+ { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
+ { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
+ { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
+ { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) },
+
+ /* Channel 2 */
+ { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
+ { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
+ { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
+ { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
+
+ /* Generic Non-core registers */
+ { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) },
+
+};
+
+#define PCI_ID_TABLE_ENTRY(A) { A, ARRAY_SIZE(A) }
+struct pci_id_table pci_dev_table[] = {
+ PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
+ PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
+ PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
+};
+
/*
* pci_device_id table for which devices we are looking for
*/
i7core_put_devices(i7core_dev);
}
-static void i7core_xeon_pci_fixup(int dev_id)
+static void __init i7core_xeon_pci_fixup(struct pci_id_table *table)
{
struct pci_dev *pdev = NULL;
int i;
* aren't announced by acpi. So, we need to use a legacy scan probing
* to detect them
*/
- pdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
- if (unlikely(!pdev)) {
- for (i = 0; i < MAX_SOCKET_BUSES; i++)
- pcibios_scan_specific_bus(255-i);
+ while (table && table->descr) {
+ pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
+ if (unlikely(!pdev)) {
+ for (i = 0; i < MAX_SOCKET_BUSES; i++)
+ pcibios_scan_specific_bus(255-i);
+ }
+ pci_dev_put(pdev);
+ table++;
}
}
+static unsigned i7core_pci_lastbus(void)
+{
+ int last_bus = 0, bus;
+ struct pci_bus *b = NULL;
+
+ while ((b = pci_find_next_bus(b)) != NULL) {
+ bus = b->number;
+ debugf0("Found bus %d\n", bus);
+ if (bus > last_bus)
+ last_bus = bus;
+ }
+
+ debugf0("Last bus %d\n", last_bus);
+
+ return last_bus;
+}
+
/*
* i7core_get_devices Find and perform 'get' operation on the MCH's
* device/functions we want to reference for this driver
* Need to 'get' device 16 func 1 and func 2
*/
int i7core_get_onedevice(struct pci_dev **prev, int devno,
- struct pci_id_descr *dev_descr, unsigned n_devs)
+ struct pci_id_descr *dev_descr, unsigned n_devs,
+ unsigned last_bus)
{
struct i7core_dev *i7core_dev;
if (dev_descr->optional)
return 0;
- i7core_printk(KERN_ERR,
+ if (devno == 0)
+ return -ENODEV;
+
+ i7core_printk(KERN_INFO,
"Device not found: dev %02x.%d PCI ID %04x:%04x\n",
dev_descr->dev, dev_descr->func,
PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
}
bus = pdev->bus->number;
- if (bus == 0x3f)
- socket = 0;
- else
- socket = 255 - bus;
+ socket = last_bus - bus;
i7core_dev = get_i7core_dev(socket);
if (!i7core_dev) {
return -ENOMEM;
i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * n_devs,
GFP_KERNEL);
- if (!i7core_dev->pdev)
+ if (!i7core_dev->pdev) {
+ kfree(i7core_dev);
return -ENOMEM;
+ }
i7core_dev->socket = socket;
i7core_dev->n_devs = n_devs;
list_add_tail(&i7core_dev->list, &i7core_edac_list);
return 0;
}
-static int i7core_get_devices(struct pci_id_descr dev_descr[], unsigned n_devs)
+static int i7core_get_devices(struct pci_id_table *table)
{
- int i, rc;
+ int i, rc, last_bus;
struct pci_dev *pdev = NULL;
-
- for (i = 0; i < n_devs; i++) {
- pdev = NULL;
- do {
- rc = i7core_get_onedevice(&pdev, i, &dev_descr[i],
- n_devs);
- if (rc < 0) {
- i7core_put_all_devices();
- return -ENODEV;
- }
- } while (pdev);
+ struct pci_id_descr *dev_descr;
+
+ last_bus = i7core_pci_lastbus();
+
+ while (table && table->descr) {
+ dev_descr = table->descr;
+ for (i = 0; i < table->n_devs; i++) {
+ pdev = NULL;
+ do {
+ rc = i7core_get_onedevice(&pdev, i,
+ &dev_descr[i],
+ table->n_devs,
+ last_bus);
+ if (rc < 0) {
+ if (i == 0) {
+ i = table->n_devs;
+ break;
+ }
+ i7core_put_all_devices();
+ return -ENODEV;
+ }
+ } while (pdev);
+ }
+ table++;
}
return 0;
+ return 0;
}
static int mci_bind_devs(struct mem_ctl_info *mci,
count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
% MCE_LOG_LEN;
if (!count)
- return;
+ goto check_ce_error;
m = pvt->mce_outentry;
if (pvt->mce_in + count > MCE_LOG_LEN) {
/*
* Now, let's increment CE error counts
*/
+check_ce_error:
if (!pvt->is_registered)
i7core_udimm_check_mc_ecc_err(mci);
else
}
fail:
- edac_mc_free(mci);
+ if (rc < 0)
+ edac_mc_free(mci);
return rc;
}
* 0 for FOUND a device
* < 0 for error code
*/
+
+static int probed = 0;
+
static int __devinit i7core_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
- int dev_idx = id->driver_data;
int rc;
struct i7core_dev *i7core_dev;
+ /* get the pci devices we want to reserve for our use */
+ mutex_lock(&i7core_edac_lock);
+
/*
* All memory controllers are allocated at the first pass.
*/
- if (unlikely(dev_idx >= 1))
+ if (unlikely(probed >= 1)) {
+ mutex_unlock(&i7core_edac_lock);
return -EINVAL;
-
- /* get the pci devices we want to reserve for our use */
- mutex_lock(&i7core_edac_lock);
-
- if (pdev->device == PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0) {
- printk(KERN_INFO "i7core_edac: detected a "
- "Lynnfield processor\n");
- rc = i7core_get_devices(pci_dev_descr_lynnfield,
- ARRAY_SIZE(pci_dev_descr_lynnfield));
- } else {
- printk(KERN_INFO "i7core_edac: detected a "
- "Nehalem/Nehalem-EP processor\n");
- rc = i7core_get_devices(pci_dev_descr_i7core,
- ARRAY_SIZE(pci_dev_descr_i7core));
}
+ probed++;
+ rc = i7core_get_devices(pci_dev_table);
if (unlikely(rc < 0))
goto fail0;
i7core_dev->socket);
}
}
+ probed--;
+
mutex_unlock(&i7core_edac_lock);
}
/* Ensure that the OPSTATE is set correctly for POLL or NMI */
opstate_init();
- i7core_xeon_pci_fixup(pci_dev_descr_i7core[0].dev_id);
+ i7core_xeon_pci_fixup(pci_dev_table);
pci_rc = pci_register_driver(&i7core_driver);
git.samba.org / sfrench / cifs-2.6.git / blobdiff