Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and 'clk...

[sfrench/cifs-2.6.git] / drivers / clk / tegra / clk-tegra124.c

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index df0018f7bf7ed8668d04a6ab5ef47994b4ef3ac3..d7bee144f4b7c40dc604f4022b6a74f0b48338ec 100644 (file)
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -413,7 +413,6 @@ static struct tegra_clk_pll_params pll_m_params = {
        .base_reg = PLLM_BASE,
        .misc_reg = PLLM_MISC,
        .lock_mask = PLL_BASE_LOCK,
-       .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
        .max_p = 5,
        .pdiv_tohw = pllm_p,
@@ -421,7 +420,7 @@ static struct tegra_clk_pll_params pll_m_params = {
        .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
        .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
        .freq_table = pll_m_freq_table,
-       .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
+       .flags = TEGRA_PLL_USE_LOCK,
 };
 
 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
@@ -1466,9 +1465,9 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
        tegra_pmc_clk_init(pmc_base, tegra124_clks);
 
        /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
-       plld_base = clk_readl(clk_base + PLLD_BASE);
+       plld_base = readl(clk_base + PLLD_BASE);
        plld_base &= ~BIT(25);
-       clk_writel(plld_base, clk_base + PLLD_BASE);
+       writel(plld_base, clk_base + PLLD_BASE);
 }
 
 /**