clk: qcom: Add support for banked MD RCGs

[sfrench/cifs-2.6.git] / drivers / clk / qcom / mmcc-msm8960.c

diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index 2e80a219b8ead315a053676f1776c39363f12fda..775e00dbcbc8da2ca777257f7b61d6df351372f5 100644 (file)
--- a/drivers/clk/qcom/mmcc-msm8960.c
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -773,9 +773,11 @@ static struct freq_tbl clk_tbl_gfx2d[] = {
 };
 
 static struct clk_dyn_rcg gfx2d0_src = {
-       .ns_reg = 0x0070,
+       .ns_reg[0] = 0x0070,
+       .ns_reg[1] = 0x0070,
        .md_reg[0] = 0x0064,
        .md_reg[1] = 0x0068,
+       .bank_reg = 0x0060,
        .mn[0] = {
                .mnctr_en_bit = 8,
                .mnctr_reset_bit = 25,
@@ -831,9 +833,11 @@ static struct clk_branch gfx2d0_clk = {
 };
 
 static struct clk_dyn_rcg gfx2d1_src = {
-       .ns_reg = 0x007c,
+       .ns_reg[0] = 0x007c,
+       .ns_reg[1] = 0x007c,
        .md_reg[0] = 0x0078,
        .md_reg[1] = 0x006c,
+       .bank_reg = 0x0074,
        .mn[0] = {
                .mnctr_en_bit = 8,
                .mnctr_reset_bit = 25,
@@ -930,9 +934,11 @@ static struct freq_tbl clk_tbl_gfx3d_8064[] = {
 };
 
 static struct clk_dyn_rcg gfx3d_src = {
-       .ns_reg = 0x008c,
+       .ns_reg[0] = 0x008c,
+       .ns_reg[1] = 0x008c,
        .md_reg[0] = 0x0084,
        .md_reg[1] = 0x0088,
+       .bank_reg = 0x0080,
        .mn[0] = {
                .mnctr_en_bit = 8,
                .mnctr_reset_bit = 25,
@@ -1006,9 +1012,11 @@ static struct freq_tbl clk_tbl_vcap[] = {
 };
 
 static struct clk_dyn_rcg vcap_src = {
-       .ns_reg = 0x021c,
+       .ns_reg[0] = 0x021c,
+       .ns_reg[1] = 0x021c,
        .md_reg[0] = 0x01ec,
        .md_reg[1] = 0x0218,
+       .bank_reg = 0x0178,
        .mn[0] = {
                .mnctr_en_bit = 8,
                .mnctr_reset_bit = 23,
@@ -1211,9 +1219,11 @@ static struct freq_tbl clk_tbl_mdp[] = {
 };
 
 static struct clk_dyn_rcg mdp_src = {
-       .ns_reg = 0x00d0,
+       .ns_reg[0] = 0x00d0,
+       .ns_reg[1] = 0x00d0,
        .md_reg[0] = 0x00c4,
        .md_reg[1] = 0x00c8,
+       .bank_reg = 0x00c0,
        .mn[0] = {
                .mnctr_en_bit = 8,
                .mnctr_reset_bit = 31,
@@ -1318,7 +1328,9 @@ static struct freq_tbl clk_tbl_rot[] = {
 };
 
 static struct clk_dyn_rcg rot_src = {
-       .ns_reg = 0x00e8,
+       .ns_reg[0] = 0x00e8,
+       .ns_reg[1] = 0x00e8,
+       .bank_reg = 0x00e8,
        .p[0] = {
                .pre_div_shift = 22,
                .pre_div_width = 4,
@@ -1542,9 +1554,11 @@ static struct freq_tbl clk_tbl_vcodec[] = {
 };
 
 static struct clk_dyn_rcg vcodec_src = {
-       .ns_reg = 0x0100,
+       .ns_reg[0] = 0x0100,
+       .ns_reg[1] = 0x0100,
        .md_reg[0] = 0x00fc,
        .md_reg[1] = 0x0128,
+       .bank_reg = 0x00f8,
        .mn[0] = {
                .mnctr_en_bit = 5,
                .mnctr_reset_bit = 31,