Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit...
[sfrench/cifs-2.6.git] / drivers / clk / qcom / gcc-sdm845.c
index c782e62dd98b8949e469cc3c0ca12eb288d0f58f..7131dcf9b0603ad6a5e4069d9367add7aa6961a1 100644 (file)
@@ -115,8 +115,8 @@ static const char * const gcc_parent_names_6[] = {
        "core_bi_pll_test_se",
 };
 
-static const char * const gcc_parent_names_7[] = {
-       "bi_tcxo",
+static const char * const gcc_parent_names_7_ao[] = {
+       "bi_tcxo_ao",
        "gpll0",
        "gpll0_out_even",
        "core_bi_pll_test_se",
@@ -128,6 +128,12 @@ static const char * const gcc_parent_names_8[] = {
        "core_bi_pll_test_se",
 };
 
+static const char * const gcc_parent_names_8_ao[] = {
+       "bi_tcxo_ao",
+       "gpll0",
+       "core_bi_pll_test_se",
+};
+
 static const struct parent_map gcc_parent_map_10[] = {
        { P_BI_TCXO, 0 },
        { P_GPLL0_OUT_MAIN, 1 },
@@ -210,7 +216,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
        .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_cpuss_ahb_clk_src",
-               .parent_names = gcc_parent_names_7,
+               .parent_names = gcc_parent_names_7_ao,
                .num_parents = 4,
                .ops = &clk_rcg2_ops,
        },
@@ -229,7 +235,7 @@ static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
        .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_cpuss_rbcpr_clk_src",
-               .parent_names = gcc_parent_names_8,
+               .parent_names = gcc_parent_names_8_ao,
                .num_parents = 3,
                .ops = &clk_rcg2_ops,
        },
@@ -1697,6 +1703,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
                .enable_mask = BIT(4),
                .hw.init = &(struct clk_init_data){
                        .name = "gcc_pcie_0_pipe_clk",
+                       .parent_names = (const char *[]){ "pcie_0_pipe_clk" },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1796,6 +1805,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
                .enable_mask = BIT(30),
                .hw.init = &(struct clk_init_data){
                        .name = "gcc_pcie_1_pipe_clk",
+                       .parent_names = (const char *[]){ "pcie_1_pipe_clk" },
+                       .num_parents = 1,
                        .ops = &clk_branch2_ops,
                },
        },