clk: meson: axg: mark fdiv2 and fdiv3 as critical

[sfrench/cifs-2.6.git] / drivers / clk / meson / axg.c

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index a5e4f7b22f39de88f2b443cd72f2ab8516c653c9..792735d7e46ea0faf3299f710813df3f98cd3834 100644 (file)
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -134,36 +134,36 @@ static struct clk_regmap axg_sys_pll = {
        },
 };
 
-static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
-       PLL_RATE(960000000, 40, 1),
-       PLL_RATE(984000000, 41, 1),
-       PLL_RATE(1008000000, 42, 1),
-       PLL_RATE(1032000000, 43, 1),
-       PLL_RATE(1056000000, 44, 1),
-       PLL_RATE(1080000000, 45, 1),
-       PLL_RATE(1104000000, 46, 1),
-       PLL_RATE(1128000000, 47, 1),
-       PLL_RATE(1152000000, 48, 1),
-       PLL_RATE(1176000000, 49, 1),
-       PLL_RATE(1200000000, 50, 1),
-       PLL_RATE(1224000000, 51, 1),
-       PLL_RATE(1248000000, 52, 1),
-       PLL_RATE(1272000000, 53, 1),
-       PLL_RATE(1296000000, 54, 1),
-       PLL_RATE(1320000000, 55, 1),
-       PLL_RATE(1344000000, 56, 1),
-       PLL_RATE(1368000000, 57, 1),
-       PLL_RATE(1392000000, 58, 1),
-       PLL_RATE(1416000000, 59, 1),
-       PLL_RATE(1440000000, 60, 1),
-       PLL_RATE(1464000000, 61, 1),
-       PLL_RATE(1488000000, 62, 1),
-       PLL_RATE(1512000000, 63, 1),
-       PLL_RATE(1536000000, 64, 1),
-       PLL_RATE(1560000000, 65, 1),
-       PLL_RATE(1584000000, 66, 1),
-       PLL_RATE(1608000000, 67, 1),
-       PLL_RATE(1632000000, 68, 1),
+static const struct pll_params_table axg_gp0_pll_params_table[] = {
+       PLL_PARAMS(40, 1),
+       PLL_PARAMS(41, 1),
+       PLL_PARAMS(42, 1),
+       PLL_PARAMS(43, 1),
+       PLL_PARAMS(44, 1),
+       PLL_PARAMS(45, 1),
+       PLL_PARAMS(46, 1),
+       PLL_PARAMS(47, 1),
+       PLL_PARAMS(48, 1),
+       PLL_PARAMS(49, 1),
+       PLL_PARAMS(50, 1),
+       PLL_PARAMS(51, 1),
+       PLL_PARAMS(52, 1),
+       PLL_PARAMS(53, 1),
+       PLL_PARAMS(54, 1),
+       PLL_PARAMS(55, 1),
+       PLL_PARAMS(56, 1),
+       PLL_PARAMS(57, 1),
+       PLL_PARAMS(58, 1),
+       PLL_PARAMS(59, 1),
+       PLL_PARAMS(60, 1),
+       PLL_PARAMS(61, 1),
+       PLL_PARAMS(62, 1),
+       PLL_PARAMS(63, 1),
+       PLL_PARAMS(64, 1),
+       PLL_PARAMS(65, 1),
+       PLL_PARAMS(66, 1),
+       PLL_PARAMS(67, 1),
+       PLL_PARAMS(68, 1),
        { /* sentinel */ },
 };
 
@@ -207,7 +207,7 @@ static struct clk_regmap axg_gp0_pll_dco = {
                        .shift   = 29,
                        .width   = 1,
                },
-               .table = axg_gp0_pll_rate_table,
+               .table = axg_gp0_pll_params_table,
                .init_regs = axg_gp0_init_regs,
                .init_count = ARRAY_SIZE(axg_gp0_init_regs),
        },
@@ -275,7 +275,7 @@ static struct clk_regmap axg_hifi_pll_dco = {
                        .shift   = 29,
                        .width   = 1,
                },
-               .table = axg_gp0_pll_rate_table,
+               .table = axg_gp0_pll_params_table,
                .init_regs = axg_hifi_init_regs,
                .init_count = ARRAY_SIZE(axg_hifi_init_regs),
                .flags = CLK_MESON_PLL_ROUND_CLOSEST,
@@ -325,6 +325,7 @@ static struct clk_regmap axg_fclk_div2 = {
                .ops = &clk_regmap_gate_ops,
                .parent_names = (const char *[]){ "fclk_div2_div" },
                .num_parents = 1,
+               .flags = CLK_IS_CRITICAL,
        },
 };
 
@@ -349,6 +350,18 @@ static struct clk_regmap axg_fclk_div3 = {
                .ops = &clk_regmap_gate_ops,
                .parent_names = (const char *[]){ "fclk_div3_div" },
                .num_parents = 1,
+               /*
+                * FIXME:
+                * This clock, as fdiv2, is used by the SCPI FW and is required
+                * by the platform to operate correctly.
+                * Until the following condition are met, we need this clock to
+                * be marked as critical:
+                * a) The SCPI generic driver claims and enable all the clocks
+                *    it needs
+                * b) CCF has a clock hand-off mechanism to make the sure the
+                *    clock stays on until the proper driver comes along
+                */
+               .flags = CLK_IS_CRITICAL,
        },
 };
 
@@ -631,11 +644,10 @@ static struct clk_regmap axg_mpll3 = {
        },
 };
 
-static const struct pll_rate_table axg_pcie_pll_rate_table[] = {
+static const struct pll_params_table axg_pcie_pll_params_table[] = {
        {
-               .rate   = 1600000000,
-               .m      = 200,
-               .n      = 3,
+               .m = 200,
+               .n = 3,
        },
        { /* sentinel */ },
 };
@@ -682,7 +694,7 @@ static struct clk_regmap axg_pcie_pll_dco = {
                        .shift   = 29,
                        .width   = 1,
                },
-               .table = axg_pcie_pll_rate_table,
+               .table = axg_pcie_pll_params_table,
                .init_regs = axg_pcie_init_regs,
                .init_count = ARRAY_SIZE(axg_pcie_init_regs),
        },
@@ -731,12 +743,14 @@ static struct clk_regmap axg_pcie_mux = {
                .offset = HHI_PCIE_PLL_CNTL6,
                .mask = 0x1,
                .shift = 2,
+               /* skip the parent mpll3, reserved for debug */
+               .table = (u32[]){ 1 },
        },
        .hw.init = &(struct clk_init_data){
                .name = "pcie_mux",
                .ops = &clk_regmap_mux_ops,
-               .parent_names = (const char *[]){ "mpll3", "pcie_pll" },
-               .num_parents = 2,
+               .parent_names = (const char *[]){ "pcie_pll" },
+               .num_parents = 1,
                .flags = CLK_SET_RATE_PARENT,
        },
 };