Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit...
[sfrench/cifs-2.6.git] / drivers / clk / mediatek / clk-mtk.h
index f83c2bbb677ea33965a7cbf0cf9671bee3fd6c1e..fb27b5bf30d95e737ffabdaf43a4ddd4d86328a0 100644 (file)
@@ -81,15 +81,13 @@ struct mtk_composite {
        signed char divider_shift;
        signed char divider_width;
 
+       u8 mux_flags;
+
        signed char num_parents;
 };
 
-/*
- * In case the rate change propagation to parent clocks is undesirable,
- * this macro allows to specify the clock flags manually.
- */
-#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width,     \
-                       _gate, _flags) {                                \
+#define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift,           \
+                               _width, _gate, _flags, _muxflags) {     \
                .id = _id,                                              \
                .name = _name,                                          \
                .mux_reg = _reg,                                        \
@@ -101,8 +99,18 @@ struct mtk_composite {
                .parent_names = _parents,                               \
                .num_parents = ARRAY_SIZE(_parents),                    \
                .flags = _flags,                                        \
+               .mux_flags = _muxflags,                                 \
        }
 
+/*
+ * In case the rate change propagation to parent clocks is undesirable,
+ * this macro allows to specify the clock flags manually.
+ */
+#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width,     \
+                       _gate, _flags)                                  \
+               MUX_GATE_FLAGS_2(_id, _name, _parents, _reg,            \
+                                       _shift, _width, _gate, _flags, 0)
+
 /*
  * Unless necessary, all MUX_GATE clocks propagate rate changes to their
  * parent clock by default.
@@ -111,7 +119,11 @@ struct mtk_composite {
        MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width,      \
                _gate, CLK_SET_RATE_PARENT)
 
-#define MUX(_id, _name, _parents, _reg, _shift, _width) {              \
+#define MUX(_id, _name, _parents, _reg, _shift, _width)                        \
+       MUX_FLAGS(_id, _name, _parents, _reg,                           \
+                 _shift, _width, CLK_SET_RATE_PARENT)
+
+#define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) {        \
                .id = _id,                                              \
                .name = _name,                                          \
                .mux_reg = _reg,                                        \
@@ -121,7 +133,7 @@ struct mtk_composite {
                .divider_shift = -1,                                    \
                .parent_names = _parents,                               \
                .num_parents = ARRAY_SIZE(_parents),                    \
-               .flags = CLK_SET_RATE_PARENT,                           \
+               .flags = _flags,                                \
        }
 
 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg,        \
@@ -158,6 +170,7 @@ struct mtk_gate {
        const struct mtk_gate_regs *regs;
        int shift;
        const struct clk_ops *ops;
+       unsigned long flags;
 };
 
 int mtk_clk_register_gates(struct device_node *node,