lib/list_sort: simplify and remove MAX_LIST_LENGTH_BITS
[sfrench/cifs-2.6.git] / drivers / clk / clk-gate.c
index f05823cd9b21117a0dd04f3d86a6a6f658cc983d..1b99fc96274517b61fb0fca61978551e50e837dc 100644 (file)
  * parent - fixed parent.  No clk_set_parent support
  */
 
+static inline u32 clk_gate_readl(struct clk_gate *gate)
+{
+       if (gate->flags & CLK_GATE_BIG_ENDIAN)
+               return ioread32be(gate->reg);
+
+       return readl(gate->reg);
+}
+
+static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
+{
+       if (gate->flags & CLK_GATE_BIG_ENDIAN)
+               iowrite32be(val, gate->reg);
+       else
+               writel(val, gate->reg);
+}
+
 /*
  * It works on following logic:
  *
@@ -55,7 +71,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
                if (set)
                        reg |= BIT(gate->bit_idx);
        } else {
-               reg = clk_readl(gate->reg);
+               reg = clk_gate_readl(gate);
 
                if (set)
                        reg |= BIT(gate->bit_idx);
@@ -63,7 +79,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
                        reg &= ~BIT(gate->bit_idx);
        }
 
-       clk_writel(reg, gate->reg);
+       clk_gate_writel(gate, reg);
 
        if (gate->lock)
                spin_unlock_irqrestore(gate->lock, flags);
@@ -88,7 +104,7 @@ int clk_gate_is_enabled(struct clk_hw *hw)
        u32 reg;
        struct clk_gate *gate = to_clk_gate(hw);
 
-       reg = clk_readl(gate->reg);
+       reg = clk_gate_readl(gate);
 
        /* if a set bit disables this clk, flip it before masking */
        if (gate->flags & CLK_GATE_SET_TO_DISABLE)
@@ -142,7 +158,7 @@ struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
 
        init.name = name;
        init.ops = &clk_gate_ops;
-       init.flags = flags | CLK_IS_BASIC;
+       init.flags = flags;
        init.parent_names = parent_name ? &parent_name : NULL;
        init.num_parents = parent_name ? 1 : 0;