#include <asm/apic.h>
#endif
-/*
- * Include the apic definitions for x86 to have the APIC timer related defines
- * available also for UP (on SMP it gets magically included via linux/smp.h).
- */
-#ifdef CONFIG_X86
-#include <asm/apic.h>
-#endif
-
#include <asm/io.h>
#include <asm/uaccess.h>
struct acpi_processor_cx *cx)
{
struct acpi_processor_power *pwr = &pr->power;
+ u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2;
/*
* Check, if one of the previous states already marked the lapic
if (pwr->timer_broadcast_on_state < state)
return;
- if (cx->type >= ACPI_STATE_C2)
+ if (cx->type >= type)
pr->power.timer_broadcast_on_state = state;
}
int sleep_ticks = 0;
u32 t1, t2 = 0;
- pr = processors[smp_processor_id()];
- if (!pr)
- return;
-
/*
* Interrupts must be disabled during bus mastering calculations and
* for C2/C3 transitions.
*/
local_irq_disable();
+ pr = processors[smp_processor_id()];
+ if (!pr) {
+ local_irq_enable();
+ return;
+ }
+
/*
* Check whether we truly need to go idle, or should
* reschedule:
#ifdef CONFIG_GENERIC_TIME
/* TSC halts in C2, so notify users */
- mark_tsc_unstable();
+ mark_tsc_unstable("possible TSC halt in C2");
#endif
/* Re-enable interrupts */
local_irq_enable();
#ifdef CONFIG_GENERIC_TIME
/* TSC halts in C3, so notify users */
- mark_tsc_unstable();
+ mark_tsc_unstable("TSC halts in C3");
#endif
/* Re-enable interrupts */
local_irq_enable();