x86: avoid back to back on_each_cpu in cpa_flush_array

[sfrench/cifs-2.6.git] / arch / x86 / mm / pageattr.c

diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 797f9f107cb6871a3797680c7dbed9430cb0f354..e17efed088c54a7b546b7b76c073ab55231d425e 100644 (file)
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -153,7 +153,7 @@ static void __cpa_flush_all(void *arg)
         */
        __flush_tlb_all();
 
-       if (cache && boot_cpu_data.x86_model >= 4)
+       if (cache && boot_cpu_data.x86 >= 4)
                wbinvd();
 }
 
@@ -208,20 +208,15 @@ static void cpa_flush_array(unsigned long *start, int numpages, int cache,
                            int in_flags, struct page **pages)
 {
        unsigned int i, level;
+       unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
 
        BUG_ON(irqs_disabled());
 
-       on_each_cpu(__cpa_flush_range, NULL, 1);
+       on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
 
-       if (!cache)
+       if (!cache || do_wbinvd)
                return;
 
-       /* 4M threshold */
-       if (numpages >= 1024) {
-               if (boot_cpu_data.x86_model >= 4)
-                       wbinvd();
-               return;
-       }
        /*
         * We only need to flush on one CPU,
         * clflush is a MESI-coherent instruction that