Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

[sfrench/cifs-2.6.git] / arch / x86 / kernel / process.c

diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index e7e35219b32f23e115c23846d06c07b0128e26ae..d401f1d2d06ef47c1dba0a33f86679a33ab24fa9 100644 (file)
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -28,6 +28,7 @@ unsigned long idle_nomwait;
 EXPORT_SYMBOL(idle_nomwait);
 
 struct kmem_cache *task_xstate_cachep;
+EXPORT_SYMBOL_GPL(task_xstate_cachep);
 
 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
 {
@@ -371,7 +372,7 @@ static inline int hlt_use_halt(void)
 void default_idle(void)
 {
        if (hlt_use_halt()) {
-               trace_power_start(POWER_CSTATE, 1);
+               trace_power_start(POWER_CSTATE, 1, smp_processor_id());
                current_thread_info()->status &= ~TS_POLLING;
                /*
                 * TS_POLLING-cleared state must be visible before we
@@ -441,7 +442,7 @@ EXPORT_SYMBOL_GPL(cpu_idle_wait);
  */
 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 {
-       trace_power_start(POWER_CSTATE, (ax>>4)+1);
+       trace_power_start(POWER_CSTATE, (ax>>4)+1, smp_processor_id());
        if (!need_resched()) {
                if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
                        clflush((void *)&current_thread_info()->flags);
@@ -457,7 +458,7 @@ void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 static void mwait_idle(void)
 {
        if (!need_resched()) {
-               trace_power_start(POWER_CSTATE, 1);
+               trace_power_start(POWER_CSTATE, 1, smp_processor_id());
                if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
                        clflush((void *)&current_thread_info()->flags);
 
@@ -478,7 +479,7 @@ static void mwait_idle(void)
  */
 static void poll_idle(void)
 {
-       trace_power_start(POWER_CSTATE, 0);
+       trace_power_start(POWER_CSTATE, 0, smp_processor_id());
        local_irq_enable();
        while (!need_resched())
                cpu_relax();
@@ -525,44 +526,10 @@ static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
        return (edx & MWAIT_EDX_C1);
 }
 
-/*
- * Check for AMD CPUs, where APIC timer interrupt does not wake up CPU from C1e.
- * For more information see
- * - Erratum #400 for NPT family 0xf and family 0x10 CPUs
- * - Erratum #365 for family 0x11 (not affected because C1e not in use)
- */
-static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
-{
-       u64 val;
-       if (c->x86_vendor != X86_VENDOR_AMD)
-               goto no_c1e_idle;
-
-       /* Family 0x0f models < rev F do not have C1E */
-       if (c->x86 == 0x0F && c->x86_model >= 0x40)
-               return 1;
-
-       if (c->x86 == 0x10) {
-               /*
-                * check OSVW bit for CPUs that are not affected
-                * by erratum #400
-                */
-               if (cpu_has(c, X86_FEATURE_OSVW)) {
-                       rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
-                       if (val >= 2) {
-                               rdmsrl(MSR_AMD64_OSVW_STATUS, val);
-                               if (!(val & BIT(1)))
-                                       goto no_c1e_idle;
-                       }
-               }
-               return 1;
-       }
-
-no_c1e_idle:
-       return 0;
-}
+bool c1e_detected;
+EXPORT_SYMBOL(c1e_detected);
 
 static cpumask_var_t c1e_mask;
-static int c1e_detected;
 
 void c1e_remove_cpu(int cpu)
 {
@@ -584,12 +551,12 @@ static void c1e_idle(void)
                u32 lo, hi;
 
                rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
+
                if (lo & K8_INTP_C1E_ACTIVE_MASK) {
-                       c1e_detected = 1;
+                       c1e_detected = true;
                        if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
                                mark_tsc_unstable("TSC halt in AMD C1E");
                        printk(KERN_INFO "System has AMD C1E enabled\n");
-                       set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
                }
        }
 
@@ -638,7 +605,8 @@ void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
                 */
                printk(KERN_INFO "using mwait in idle threads.\n");
                pm_idle = mwait_idle;
-       } else if (check_c1e_idle(c)) {
+       } else if (cpu_has_amd_erratum(amd_erratum_400)) {
+               /* E400: APIC timer interrupt does not wake up CPU from C1e */
                printk(KERN_INFO "using C1E aware idle routine\n");
                pm_idle = c1e_idle;
        } else