x86: print message if nmi_watchdog=2 cannot be enabled

[sfrench/cifs-2.6.git] / arch / x86 / kernel / cpu / perfctr-watchdog.c

diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index 93fecd4b03de0dd99185362e8a2495d7e5e00ccc..b943e10ad81438aa528ee1c7dad5f7a528488a38 100644 (file)
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -34,7 +34,7 @@ struct wd_ops {
        u64 checkbit;
 };
 
-static struct wd_ops *wd_ops;
+static const struct wd_ops *wd_ops;
 
 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
  * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
@@ -120,7 +120,9 @@ int reserve_perfctr_nmi(unsigned int msr)
        unsigned int counter;
 
        counter = nmi_perfctr_msr_to_bit(msr);
-       BUG_ON(counter > NMI_MAX_COUNTER_BITS);
+       /* register not managed by the allocator? */
+       if (counter > NMI_MAX_COUNTER_BITS)
+               return 1;
 
        if (!test_and_set_bit(counter, perfctr_nmi_owner))
                return 1;
@@ -132,7 +134,9 @@ void release_perfctr_nmi(unsigned int msr)
        unsigned int counter;
 
        counter = nmi_perfctr_msr_to_bit(msr);
-       BUG_ON(counter > NMI_MAX_COUNTER_BITS);
+       /* register not managed by the allocator? */
+       if (counter > NMI_MAX_COUNTER_BITS)
+               return;
 
        clear_bit(counter, perfctr_nmi_owner);
 }
@@ -142,7 +146,9 @@ int reserve_evntsel_nmi(unsigned int msr)
        unsigned int counter;
 
        counter = nmi_evntsel_msr_to_bit(msr);
-       BUG_ON(counter > NMI_MAX_COUNTER_BITS);
+       /* register not managed by the allocator? */
+       if (counter > NMI_MAX_COUNTER_BITS)
+               return 1;
 
        if (!test_and_set_bit(counter, evntsel_nmi_owner))
                return 1;
@@ -154,12 +160,13 @@ void release_evntsel_nmi(unsigned int msr)
        unsigned int counter;
 
        counter = nmi_evntsel_msr_to_bit(msr);
-       BUG_ON(counter > NMI_MAX_COUNTER_BITS);
+       /* register not managed by the allocator? */
+       if (counter > NMI_MAX_COUNTER_BITS)
+               return;
 
        clear_bit(counter, evntsel_nmi_owner);
 }
 
-EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
 EXPORT_SYMBOL(reserve_perfctr_nmi);
 EXPORT_SYMBOL(release_perfctr_nmi);
@@ -317,7 +324,7 @@ static void single_msr_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
        write_watchdog_counter(wd->perfctr_msr, NULL, nmi_hz);
 }
 
-static struct wd_ops k7_wd_ops = {
+static const struct wd_ops k7_wd_ops = {
        .reserve = single_msr_reserve,
        .unreserve = single_msr_unreserve,
        .setup = setup_k7_watchdog,
@@ -380,7 +387,7 @@ static void p6_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
        write_watchdog_counter32(wd->perfctr_msr, NULL,nmi_hz);
 }
 
-static struct wd_ops p6_wd_ops = {
+static const struct wd_ops p6_wd_ops = {
        .reserve = single_msr_reserve,
        .unreserve = single_msr_unreserve,
        .setup = setup_p6_watchdog,
@@ -532,7 +539,7 @@ static void p4_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
        write_watchdog_counter(wd->perfctr_msr, NULL, nmi_hz);
 }
 
-static struct wd_ops p4_wd_ops = {
+static const struct wd_ops p4_wd_ops = {
        .reserve = p4_reserve,
        .unreserve = p4_unreserve,
        .setup = setup_p4_watchdog,
@@ -550,6 +557,8 @@ static struct wd_ops p4_wd_ops = {
 #define ARCH_PERFMON_NMI_EVENT_SEL     ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
 #define ARCH_PERFMON_NMI_EVENT_UMASK   ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
 
+static struct wd_ops intel_arch_wd_ops;
+
 static int setup_intel_arch_watchdog(unsigned nmi_hz)
 {
        unsigned int ebx;
@@ -591,11 +600,11 @@ static int setup_intel_arch_watchdog(unsigned nmi_hz)
        wd->perfctr_msr = perfctr_msr;
        wd->evntsel_msr = evntsel_msr;
        wd->cccr_msr = 0;  //unused
-       wd_ops->checkbit = 1ULL << (eax.split.bit_width - 1);
+       intel_arch_wd_ops.checkbit = 1ULL << (eax.split.bit_width - 1);
        return 1;
 }
 
-static struct wd_ops intel_arch_wd_ops = {
+static struct wd_ops intel_arch_wd_ops __read_mostly = {
        .reserve = single_msr_reserve,
        .unreserve = single_msr_unreserve,
        .setup = setup_intel_arch_watchdog,
@@ -643,9 +652,6 @@ static void probe_nmi_watchdog(void)
                        wd_ops = &p6_wd_ops;
                        break;
                case 15:
-                       if (boot_cpu_data.x86_model > 0x4)
-                               return;
-
                        wd_ops = &p4_wd_ops;
                        break;
                default:
@@ -661,8 +667,10 @@ int lapic_watchdog_init(unsigned nmi_hz)
 {
        if (!wd_ops) {
                probe_nmi_watchdog();
-               if (!wd_ops)
+               if (!wd_ops) {
+                       printk(KERN_INFO "NMI watchdog: CPU not supported\n");
                        return -1;
+               }
 
                if (!wd_ops->reserve()) {
                        printk(KERN_ERR