Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6

[sfrench/cifs-2.6.git] / arch / x86 / kernel / cpu / intel.c

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 43c1dcf0bec7a6ead00d7e62fd4e3fce50b6f1b7..24ff26a38adecff5ef27d4e76fb74caebd1fbb88 100644 (file)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -29,14 +29,17 @@
 
 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 {
-       u64 misc_enable;
-
-       /* Unmask CPUID levels if masked */
-       if (!rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_enable) &&
-           (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)) {
-               misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
-               wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
-               c->cpuid_level = cpuid_eax(0);
+       /* Unmask CPUID levels if masked: */
+       if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
+               u64 misc_enable;
+
+               rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+
+               if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
+                       misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
+                       wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+                       c->cpuid_level = cpuid_eax(0);
+               }
        }
 
        if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
@@ -288,6 +291,9 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
                ds_init_intel(c);
        }
 
+       if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
+               set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
+
 #ifdef CONFIG_X86_64
        if (c->x86 == 15)
                c->x86_cache_alignment = c->x86_clflush_size * 2;