Merge branch 'core/percpu' into percpu-cpumask-x86-for-linus-2

[sfrench/cifs-2.6.git] / arch / x86 / kernel / cpu / intel.c

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 5fff00c70de0d1d8ddd3e3ce1ecad2ecec147247..1a89a2b68d1539a92939e4d33747a1bcd916390c 100644 (file)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -25,7 +25,6 @@
 #ifdef CONFIG_X86_LOCAL_APIC
 #include <asm/mpspec.h>
 #include <asm/apic.h>
-#include <mach_apic.h>
 #endif
 
 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
@@ -69,6 +68,18 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
                sched_clock_stable = 1;
        }
 
+       /*
+        * There is a known erratum on Pentium III and Core Solo
+        * and Core Duo CPUs.
+        * " Page with PAT set to WC while associated MTRR is UC
+        *   may consolidate to UC "
+        * Because of this erratum, it is better to stick with
+        * setting WC in MTRR rather than using PAT on these CPUs.
+        *
+        * Enable PAT WC only on P4, Core 2 or later CPUs.
+        */
+       if (c->x86 == 6 && c->x86_model < 15)
+               clear_cpu_cap(c, X86_FEATURE_PAT);
 }
 
 #ifdef CONFIG_X86_32
@@ -141,10 +152,10 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
         */
        if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
                rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
-               if ((lo & (1<<9)) == 0) {
+               if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
                        printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
                        printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
-                       lo |= (1<<9);   /* Disable hw prefetching */
+                       lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
                        wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
                }
        }