Merge branch 'next-general' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...

[sfrench/cifs-2.6.git] / arch / x86 / include / asm / sync_bitops.h

diff --git a/arch/x86/include/asm/sync_bitops.h b/arch/x86/include/asm/sync_bitops.h
index 2fe745356fb119d1dc9497c00caeccb3a04ab5c3..6d8d6bc183b7421ddfc367062b1ebb7164245ee3 100644 (file)
--- a/arch/x86/include/asm/sync_bitops.h
+++ b/arch/x86/include/asm/sync_bitops.h
@@ -14,6 +14,8 @@
  * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
  */
 
+#include <asm/rmwcc.h>
+
 #define ADDR (*(volatile long *)addr)
 
 /**
@@ -29,7 +31,7 @@
  */
 static inline void sync_set_bit(long nr, volatile unsigned long *addr)
 {
-       asm volatile("lock; bts %1,%0"
+       asm volatile("lock; " __ASM_SIZE(bts) " %1,%0"
                     : "+m" (ADDR)
                     : "Ir" (nr)
                     : "memory");
@@ -47,7 +49,7 @@ static inline void sync_set_bit(long nr, volatile unsigned long *addr)
  */
 static inline void sync_clear_bit(long nr, volatile unsigned long *addr)
 {
-       asm volatile("lock; btr %1,%0"
+       asm volatile("lock; " __ASM_SIZE(btr) " %1,%0"
                     : "+m" (ADDR)
                     : "Ir" (nr)
                     : "memory");
@@ -64,7 +66,7 @@ static inline void sync_clear_bit(long nr, volatile unsigned long *addr)
  */
 static inline void sync_change_bit(long nr, volatile unsigned long *addr)
 {
-       asm volatile("lock; btc %1,%0"
+       asm volatile("lock; " __ASM_SIZE(btc) " %1,%0"
                     : "+m" (ADDR)
                     : "Ir" (nr)
                     : "memory");
@@ -78,14 +80,9 @@ static inline void sync_change_bit(long nr, volatile unsigned long *addr)
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
-static inline int sync_test_and_set_bit(long nr, volatile unsigned long *addr)
+static inline bool sync_test_and_set_bit(long nr, volatile unsigned long *addr)
 {
-       unsigned char oldbit;
-
-       asm volatile("lock; bts %2,%1\n\tsetc %0"
-                    : "=qm" (oldbit), "+m" (ADDR)
-                    : "Ir" (nr) : "memory");
-       return oldbit;
+       return GEN_BINARY_RMWcc("lock; " __ASM_SIZE(bts), *addr, c, "Ir", nr);
 }
 
 /**
@@ -98,12 +95,7 @@ static inline int sync_test_and_set_bit(long nr, volatile unsigned long *addr)
  */
 static inline int sync_test_and_clear_bit(long nr, volatile unsigned long *addr)
 {
-       unsigned char oldbit;
-
-       asm volatile("lock; btr %2,%1\n\tsetc %0"
-                    : "=qm" (oldbit), "+m" (ADDR)
-                    : "Ir" (nr) : "memory");
-       return oldbit;
+       return GEN_BINARY_RMWcc("lock; " __ASM_SIZE(btr), *addr, c, "Ir", nr);
 }
 
 /**
@@ -116,12 +108,7 @@ static inline int sync_test_and_clear_bit(long nr, volatile unsigned long *addr)
  */
 static inline int sync_test_and_change_bit(long nr, volatile unsigned long *addr)
 {
-       unsigned char oldbit;
-
-       asm volatile("lock; btc %2,%1\n\tsetc %0"
-                    : "=qm" (oldbit), "+m" (ADDR)
-                    : "Ir" (nr) : "memory");
-       return oldbit;
+       return GEN_BINARY_RMWcc("lock; " __ASM_SIZE(btc), *addr, c, "Ir", nr);
 }
 
 #define sync_test_bit(nr, addr) test_bit(nr, addr)