Merge branch 'x86-tsx-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

[sfrench/cifs-2.6.git] / arch / x86 / events / perf_event.h

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 7e75f474b076518e4bb512655224ef1e059e336c..b04ae6c8775e0e298726b9414e2a07b31edbdfb9 100644 (file)
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -242,6 +242,11 @@ struct cpu_hw_events {
        struct intel_excl_cntrs         *excl_cntrs;
        int excl_thread_id; /* 0 or 1 */
 
+       /*
+        * SKL TSX_FORCE_ABORT shadow
+        */
+       u64                             tfa_shadow;
+
        /*
         * AMD specific bits
         */
@@ -682,6 +687,7 @@ do {                                                                        \
 #define PMU_FL_EXCL_CNTRS      0x4 /* has exclusive counter requirements  */
 #define PMU_FL_EXCL_ENABLED    0x8 /* exclusive counter active */
 #define PMU_FL_PEBS_ALL                0x10 /* all events are valid PEBS events */
+#define PMU_FL_TFA             0x20 /* deal with TSX force abort */
 
 #define EVENT_VAR(_id)  event_attr_##_id
 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
@@ -890,7 +896,8 @@ struct event_constraint *
 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
                          struct perf_event *event);
 
-struct intel_shared_regs *allocate_shared_regs(int cpu);
+extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu);
+extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
 
 int intel_pmu_init(void);
 
@@ -1026,9 +1033,13 @@ static inline int intel_pmu_init(void)
        return 0;
 }
 
-static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
+static inline int intel_cpuc_prepare(struct cpu_hw_event *cpuc, int cpu)
+{
+       return 0;
+}
+
+static inline void intel_cpuc_finish(struct cpu_hw_event *cpuc)
 {
-       return NULL;
 }
 
 static inline int is_ht_workaround_enabled(void)