config SH_CLK_CPG_LEGACY
depends on SH_CLK_CPG
- def_bool y if !CPU_SUBTYPE_SH7785
+ def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE
config SH_CLK_MD
int "CPU Mode Pin Setting"
LLSC, this should be more efficient than the other alternative of
disabling interrupts around the atomic sequence.
+config SPARSE_IRQ
+ bool "Support sparse irq numbering"
+ depends on EXPERIMENTAL
+ help
+ This enables support for sparse irqs. This is useful in general
+ as most CPUs have a fairly sparse array of IRQ vectors, which
+ the irq_desc then maps directly on to. Systems with a high
+ number of off-chip IRQs will want to treat this as
+ experimental until they have been independently verified.
+
+ If you don't know what to do here, say N.
+
endmenu
menu "Boot options"