*/
static unsigned long psurge_smp_message[NR_CPUS];
-void psurge_smp_message_recv(struct pt_regs *regs)
+void psurge_smp_message_recv(void)
{
int cpu = smp_processor_id();
int msg;
/* make sure there is a message there */
for (msg = 0; msg < 4; msg++)
if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
- smp_message_recv(msg, regs);
+ smp_message_recv(msg);
}
-irqreturn_t psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
+irqreturn_t psurge_primary_intr(int irq, void *d)
{
- psurge_smp_message_recv(regs);
+ psurge_smp_message_recv();
return IRQ_HANDLED;
}
static int __init smp_psurge_probe(void)
{
int i, ncpus;
+ struct device_node *dn;
/* We don't do SMP on the PPC601 -- paulus */
if (PVR_VER(mfspr(SPRN_PVR)) == 1)
* in the hammerhead memory controller in the case of the
* dual-cpu powersurge board. -- paulus.
*/
- if (find_devices("hammerhead") == NULL)
+ dn = of_find_node_by_name(NULL, "hammerhead");
+ if (dn == NULL)
return 1;
+ of_node_put(dn);
hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
{
unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
unsigned long a;
+ int i;
/* may need to flush here if secondary bats aren't setup */
for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
mb();
psurge_set_ipi(nr);
- udelay(10);
+ /*
+ * We can't use udelay here because the timebase is now frozen.
+ */
+ for (i = 0; i < 2000; ++i)
+ barrier();
psurge_clr_ipi(nr);
if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc);
if (pmac_tb_clock_chip_host == NULL)
continue;
- reg = get_property(cc, "reg", NULL);
+ reg = of_get_property(cc, "reg", NULL);
if (reg == NULL)
continue;
switch (*reg) {
struct device_node *cpus =
of_find_node_by_path("/cpus");
if (cpus &&
- get_property(cpus, "platform-cpu-timebase", NULL)) {
+ of_get_property(cpus, "platform-cpu-timebase", NULL)) {
pmac_tb_freeze = smp_core99_pfunc_tb_freeze;
printk(KERN_INFO "Processor timebase sync using"
" platform function\n");
/* GPIO based HW sync on ppc32 Core99 */
if (pmac_tb_freeze == NULL && !machine_is_compatible("MacRISC4")) {
struct device_node *cpu;
- u32 *tbprop = NULL;
+ const u32 *tbprop = NULL;
core99_tb_gpio = KL_GPIO_TB_ENABLE; /* default value */
cpu = of_find_node_by_type(NULL, "cpu");
if (cpu != NULL) {
- tbprop = get_property(cpu, "timebase-enable", NULL);
+ tbprop = of_get_property(cpu, "timebase-enable", NULL);
if (tbprop)
core99_tb_gpio = *tbprop;
of_node_put(cpu);
ppc_md.progress("smp_core99_kick_cpu", 0x346);
local_irq_save(flags);
- local_irq_disable();
/* Save reset vector */
save_vector = *vector;