Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

[sfrench/cifs-2.6.git] / arch / powerpc / platforms / chrp / pci.c

diff --git a/arch/powerpc/platforms/chrp/pci.c b/arch/powerpc/platforms/chrp/pci.c
index 28d1647b204e70b2f91462463d05f8309c136a99..0340a342f7726c8a721eacf36491f2c604d50cce 100644 (file)
--- a/arch/powerpc/platforms/chrp/pci.c
+++ b/arch/powerpc/platforms/chrp/pci.c
@@ -13,7 +13,6 @@
 #include <asm/irq.h>
 #include <asm/hydra.h>
 #include <asm/prom.h>
-#include <asm/gg2.h>
 #include <asm/machdep.h>
 #include <asm/sections.h>
 #include <asm/pci-bridge.h>
@@ -21,6 +20,7 @@
 #include <asm/rtas.h>
 
 #include "chrp.h"
+#include "gg2.h"
 
 /* LongTrail */
 void __iomem *gg2_pci_config_base;
@@ -86,8 +86,8 @@ int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
 
 static struct pci_ops gg2_pci_ops =
 {
-       gg2_read_config,
-       gg2_write_config
+       .read = gg2_read_config,
+       .write = gg2_write_config,
 };
 
 /*
@@ -124,8 +124,8 @@ int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
 
 static struct pci_ops rtas_pci_ops =
 {
-       rtas_read_config,
-       rtas_write_config
+       .read = rtas_read_config,
+       .write = rtas_write_config,
 };
 
 volatile struct Hydra __iomem *Hydra = NULL;
@@ -317,8 +317,12 @@ chrp_find_bridges(void)
 /* SL82C105 IDE Control/Status Register */
 #define SL82C105_IDECSR                0x40
 
-/* Fixup for Winbond ATA quirk, required for briq */
-void chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105)
+/* Fixup for Winbond ATA quirk, required for briq mostly because the
+ * 8259 is configured for level sensitive IRQ 14 and so wants the
+ * ATA controller to be set to fully native mode or bad things
+ * will happen.
+ */
+static void __devinit chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105)
 {
        u8 progif;
 
@@ -334,7 +338,41 @@ void chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105)
                sl82c105->class |= 0x05;
                /* Disable SL82C105 second port */
                pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0003);
+               /* Clear IO BARs, they will be reassigned */
+               pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_0, 0);
+               pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_1, 0);
+               pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_2, 0);
+               pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_3, 0);
        }
 }
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
-               chrp_pci_fixup_winbond_ata);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
+                       chrp_pci_fixup_winbond_ata);
+
+/* Pegasos2 firmware version 20040810 configures the built-in IDE controller
+ * in legacy mode, but sets the PCI registers to PCI native mode.
+ * The chip can only operate in legacy mode, so force the PCI class into legacy
+ * mode as well. The same fixup must be done to the class-code property in
+ * the IDE node /pci@80000000/ide@C,1
+ */
+static void __devinit chrp_pci_fixup_vt8231_ata(struct pci_dev *viaide)
+{
+       u8 progif;
+       struct pci_dev *viaisa;
+
+       if (!machine_is(chrp) || _chrp_type != _CHRP_Pegasos)
+               return;
+       if (viaide->irq != 14)
+               return;
+
+       viaisa = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
+       if (!viaisa)
+               return;
+       printk("Fixing VIA IDE, force legacy mode on '%s'\n", viaide->dev.bus_id);
+
+       pci_read_config_byte(viaide, PCI_CLASS_PROG, &progif);
+       pci_write_config_byte(viaide, PCI_CLASS_PROG, progif & ~0x5);
+       viaide->class &= ~0x5;
+
+       pci_dev_put(viaisa);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, chrp_pci_fixup_vt8231_ata);