Merge branch 'nvme-4.18' of git://git.infradead.org/nvme into for-linus

[sfrench/cifs-2.6.git] / arch / powerpc / perf / isa207-common.h

diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h
index 6c737d675792ed6a7e513fb0729aec1698875d02..6a0b586c935abe1d8efb70e5fcf3f7fdb88663ff 100644 (file)
--- a/arch/powerpc/perf/isa207-common.h
+++ b/arch/powerpc/perf/isa207-common.h
@@ -17,70 +17,6 @@
 #include <asm/firmware.h>
 #include <asm/cputable.h>
 
-/*
- * Raw event encoding for PowerISA v2.07:
- *
- *        60        56        52        48        44        40        36        32
- * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
- *   | | [ ]                           [      thresh_cmp     ]   [  thresh_ctl   ]
- *   | |  |                                                              |
- *   | |  *- IFM (Linux)                 thresh start/stop OR FAB match -*
- *   | *- BHRB (Linux)
- *   *- EBB (Linux)
- *
- *        28        24        20        16        12         8         4         0
- * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
- *   [   ] [  sample ]   [cache]   [ pmc ]   [unit ]   c     m   [    pmcxsel    ]
- *     |        |           |                          |     |
- *     |        |           |                          |     *- mark
- *     |        |           *- L1/L2/L3 cache_sel      |
- *     |        |                                      |
- *     |        *- sampling mode for marked events     *- combine
- *     |
- *     *- thresh_sel
- *
- * Below uses IBM bit numbering.
- *
- * MMCR1[x:y] = unit    (PMCxUNIT)
- * MMCR1[x]   = combine (PMCxCOMB)
- *
- * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
- *     # PM_MRK_FAB_RSP_MATCH
- *     MMCR1[20:27] = thresh_ctl   (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
- * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
- *     # PM_MRK_FAB_RSP_MATCH_CYC
- *     MMCR1[20:27] = thresh_ctl   (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
- * else
- *     MMCRA[48:55] = thresh_ctl   (THRESH START/END)
- *
- * if thresh_sel:
- *     MMCRA[45:47] = thresh_sel
- *
- * if thresh_cmp:
- *     MMCRA[22:24] = thresh_cmp[0:2]
- *     MMCRA[25:31] = thresh_cmp[3:9]
- *
- * if unit == 6 or unit == 7
- *     MMCRC[53:55] = cache_sel[1:3]      (L2EVENT_SEL)
- * else if unit == 8 or unit == 9:
- *     if cache_sel[0] == 0: # L3 bank
- *             MMCRC[47:49] = cache_sel[1:3]  (L3EVENT_SEL0)
- *     else if cache_sel[0] == 1:
- *             MMCRC[50:51] = cache_sel[2:3]  (L3EVENT_SEL1)
- * else if cache_sel[1]: # L1 event
- *     MMCR1[16] = cache_sel[2]
- *    MMCR1[17] = cache_sel[3]
- *
- * if mark:
- *     MMCRA[63]    = 1                (SAMPLE_ENABLE)
- *     MMCRA[57:59] = sample[0:2]      (RAND_SAMP_ELIG)
- *    MMCRA[61:62] = sample[3:4]      (RAND_SAMP_MODE)
- *
- * if EBB and BHRB:
- *     MMCRA[32:33] = IFM
- *
- */
-
 #define EVENT_EBB_MASK         1ull
 #define EVENT_EBB_SHIFT                PERF_EVENT_CONFIG_EBB_SHIFT
 #define EVENT_BHRB_MASK                1ull