Pull thermal into release branch

[sfrench/cifs-2.6.git] / arch / powerpc / mm / hash_low_32.S

diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S
index ea469eefa14603b82070efc9a7cf2cf18e52f96a..ddceefc06ecc0a5554a650e5dbe690959274943a 100644 (file)
--- a/arch/powerpc/mm/hash_low_32.S
+++ b/arch/powerpc/mm/hash_low_32.S
@@ -21,7 +21,6 @@
  *
  */
 
-#include <linux/config.h>
 #include <asm/reg.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
@@ -74,12 +73,6 @@ _GLOBAL(hash_page_sync)
  */
        .text
 _GLOBAL(hash_page)
-#ifdef CONFIG_PPC64BRIDGE
-       mfmsr   r0
-       clrldi  r0,r0,1         /* make sure it's in 32-bit mode */
-       MTMSRD(r0)
-       isync
-#endif
        tophys(r7,0)                    /* gets -KERNELBASE into r7 */
 #ifdef CONFIG_SMP
        addis   r8,r7,mmu_hash_lock@h
@@ -285,12 +278,12 @@ Hash_base = 0xc0180000
 Hash_bits = 12                         /* e.g. 256kB hash table */
 Hash_msk = (((1 << Hash_bits) - 1) * 64)
 
-#ifndef CONFIG_PPC64BRIDGE
 /* defines for the PTE format for 32-bit PPCs */
 #define PTE_SIZE       8
 #define PTEG_SIZE      64
 #define LG_PTEG_SIZE   6
 #define LDPTEu         lwzu
+#define LDPTE          lwz
 #define STPTE          stw
 #define CMPPTE         cmpw
 #define PTE_H          0x40
@@ -299,21 +292,6 @@ Hash_msk = (((1 << Hash_bits) - 1) * 64)
 #define SET_V(r)       oris r,r,PTE_V@h
 #define CLR_V(r,t)     rlwinm r,r,0,1,31
 
-#else
-/* defines for the PTE format for 64-bit PPCs */
-#define PTE_SIZE       16
-#define PTEG_SIZE      128
-#define LG_PTEG_SIZE   7
-#define LDPTEu         ldu
-#define STPTE          std
-#define CMPPTE         cmpd
-#define PTE_H          2
-#define PTE_V          1
-#define TST_V(r)       andi. r,r,PTE_V
-#define SET_V(r)       ori r,r,PTE_V
-#define CLR_V(r,t)     li t,PTE_V; andc r,r,t
-#endif /* CONFIG_PPC64BRIDGE */
-
 #define HASH_LEFT      31-(LG_PTEG_SIZE+Hash_bits-1)
 #define HASH_RIGHT     31-LG_PTEG_SIZE
 
@@ -331,14 +309,8 @@ BEGIN_FTR_SECTION
 END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT)
 
        /* Construct the high word of the PPC-style PTE (r5) */
-#ifndef CONFIG_PPC64BRIDGE
        rlwinm  r5,r3,7,1,24            /* put VSID in 0x7fffff80 bits */
        rlwimi  r5,r4,10,26,31          /* put in API (abbrev page index) */
-#else /* CONFIG_PPC64BRIDGE */
-       clrlwi  r3,r3,8                 /* reduce vsid to 24 bits */
-       sldi    r5,r3,12                /* shift vsid into position */
-       rlwimi  r5,r4,16,20,24          /* put in API (abbrev page index) */
-#endif /* CONFIG_PPC64BRIDGE */
        SET_V(r5)                       /* set V (valid) bit */
 
        /* Get the address of the primary PTE group in the hash table (r3) */
@@ -418,13 +390,30 @@ _GLOBAL(hash_page_patch_C)
         * and we know there is a definite (although small) speed
         * advantage to putting the PTE in the primary PTEG, we always
         * put the PTE in the primary PTEG.
+        *
+        * In addition, we skip any slot that is mapping kernel text in
+        * order to avoid a deadlock when not using BAT mappings if
+        * trying to hash in the kernel hash code itself after it has
+        * already taken the hash table lock. This works in conjunction
+        * with pre-faulting of the kernel text.
+        *
+        * If the hash table bucket is full of kernel text entries, we'll
+        * lockup here but that shouldn't happen
         */
-       addis   r4,r7,next_slot@ha
+
+1:     addis   r4,r7,next_slot@ha              /* get next evict slot */
        lwz     r6,next_slot@l(r4)
-       addi    r6,r6,PTE_SIZE
+       addi    r6,r6,PTE_SIZE                  /* search for candidate */
        andi.   r6,r6,7*PTE_SIZE
        stw     r6,next_slot@l(r4)
        add     r4,r3,r6
+       LDPTE   r0,PTE_SIZE/2(r4)               /* get PTE second word */
+       clrrwi  r0,r0,12
+       lis     r6,etext@h
+       ori     r6,r6,etext@l                   /* get etext */
+       tophys(r6,r6)
+       cmpl    cr0,r0,r6                       /* compare and try again */
+       blt     1b
 
 #ifndef CONFIG_SMP
        /* Store PTE in PTEG */
@@ -516,14 +505,8 @@ _GLOBAL(flush_hash_pages)
        add     r3,r3,r0                /* note code below trims to 24 bits */
 
        /* Construct the high word of the PPC-style PTE (r11) */
-#ifndef CONFIG_PPC64BRIDGE
        rlwinm  r11,r3,7,1,24           /* put VSID in 0x7fffff80 bits */
        rlwimi  r11,r4,10,26,31         /* put in API (abbrev page index) */
-#else /* CONFIG_PPC64BRIDGE */
-       clrlwi  r3,r3,8                 /* reduce vsid to 24 bits */
-       sldi    r11,r3,12               /* shift vsid into position */
-       rlwimi  r11,r4,16,20,24         /* put in API (abbrev page index) */
-#endif /* CONFIG_PPC64BRIDGE */
        SET_V(r11)                      /* set V (valid) bit */
 
 #ifdef CONFIG_SMP