Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux...

[sfrench/cifs-2.6.git] / arch / powerpc / kernel / traps.c

diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index ec74e203ee04e5b8e7e307df28c133b6226cd487..13c9dcdcba6922e32d4c00267201f47e9498f805 100644 (file)
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -437,6 +437,7 @@ static inline int check_io_access(struct pt_regs *regs)
 int machine_check_e500mc(struct pt_regs *regs)
 {
        unsigned long mcsr = mfspr(SPRN_MCSR);
+       unsigned long pvr = mfspr(SPRN_PVR);
        unsigned long reason = mcsr;
        int recoverable = 1;
 
@@ -478,8 +479,15 @@ int machine_check_e500mc(struct pt_regs *regs)
                 * may still get logged and cause a machine check.  We should
                 * only treat the non-write shadow case as non-recoverable.
                 */
-               if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
-                       recoverable = 0;
+               /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
+                * is not implemented but L1 data cache always runs in write
+                * shadow mode. Hence on data cache parity errors HW will
+                * automatically invalidate the L1 Data Cache.
+                */
+               if (PVR_VER(pvr) != PVR_VER_E6500) {
+                       if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
+                               recoverable = 0;
+               }
        }
 
        if (reason & MCSR_L2MMU_MHIT) {